xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

Bläddra i källkod 
Conflicts:
	drivers/mtd/mtdcore.c

Merged in order that I can apply the Nomadik nand/onenand support patches.
This commit is contained in:
David Woodhouse
2009-09-20 05:55:36 -07:00
förälder 304e6d5fe2 78f28b7c55
incheckning 6469f540ea
6530 ändrade filer med 703226 tillägg och 367919 borttagningar
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9
arch/arm/mach-omap2/Kconfig
Visa fil

@@ -31,6 +31,11 @@ config MACH_OMAP_GENERIC
bool "Generic OMAP board"
depends on ARCH_OMAP2 && ARCH_OMAP24XX
config MACH_OMAP2_TUSB6010
bool
depends on ARCH_OMAP2 && ARCH_OMAP2420
default y if MACH_NOKIA_N8X0
config MACH_OMAP_H4
bool "OMAP 2420 H4 board"
depends on ARCH_OMAP2 && ARCH_OMAP24XX
@@ -68,6 +73,10 @@ config MACH_OMAP_3430SDP
bool "OMAP 3430 SDP board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
config MACH_NOKIA_N8X0
bool "Nokia N800/N810"
depends on ARCH_OMAP2420
config MACH_NOKIA_RX51
bool "Nokia RX-51 board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX

10
arch/arm/mach-omap2/Makefile
Visa fil

@@ -5,7 +5,7 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
omap-2-3-common = irq.o sdrc.o
omap-2-3-common = irq.o sdrc.o omap_hwmod.o
prcm-common = prcm.o powerdomain.o
clock-common = clock.o clockdomain.o
@@ -35,6 +35,11 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
endif
# PRCM
obj-$(CONFIG_ARCH_OMAP2) += cm.o
obj-$(CONFIG_ARCH_OMAP3) += cm.o
obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o
@@ -62,7 +67,7 @@ obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \
mmc-twl4030.o
obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \
mmc-twl4030.o
obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
board-rx51-peripherals.o \
mmc-twl4030.o
@@ -74,6 +79,7 @@ obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
# Platform specific device init code
obj-y += usb-musb.o
obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o
onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o
obj-y += $(onenand-m) $(onenand-y)

18
arch/arm/mach-omap2/board-2430sdp.c
Visa fil

@@ -139,23 +139,19 @@ static inline void board_smc91x_init(void)
#endif
static struct omap_board_config_kernel sdp2430_config[] = {
{OMAP_TAG_LCD, &sdp2430_lcd_config},
};
static void __init omap_2430sdp_init_irq(void)
{
omap_board_config = sdp2430_config;
omap_board_config_size = ARRAY_SIZE(sdp2430_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
}
static struct omap_uart_config sdp2430_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel sdp2430_config[] = {
{OMAP_TAG_UART, &sdp2430_uart_config},
{OMAP_TAG_LCD, &sdp2430_lcd_config},
};
static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
@@ -205,8 +201,6 @@ static void __init omap_2430sdp_init(void)
omap2430_i2c_init();
platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
omap_board_config = sdp2430_config;
omap_board_config_size = ARRAY_SIZE(sdp2430_config);
omap_serial_init();
twl4030_mmc_init(mmc);
usb_musb_init();

29
arch/arm/mach-omap2/board-3430sdp.c
Visa fil

@@ -167,26 +167,23 @@ static struct platform_device *sdp3430_devices[] __initdata = {
&sdp3430_lcd_device,
};
static void __init omap_3430sdp_init_irq(void)
{
omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
omap_init_irq();
omap_gpio_init();
}
static struct omap_uart_config sdp3430_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_lcd_config sdp3430_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel sdp3430_config[] __initdata = {
{ OMAP_TAG_UART, &sdp3430_uart_config },
{ OMAP_TAG_LCD, &sdp3430_lcd_config },
};
static void __init omap_3430sdp_init_irq(void)
{
omap_board_config = sdp3430_config;
omap_board_config_size = ARRAY_SIZE(sdp3430_config);
omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
omap_init_irq();
omap_gpio_init();
}
static int sdp3430_batt_table[] = {
/* 0 C*/
30800, 29500, 28300, 27100,
@@ -478,12 +475,15 @@ static inline void board_smc91x_init(void)
#endif
static void enable_board_wakeup_source(void)
{
omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
}
static void __init omap_3430sdp_init(void)
{
omap3430_i2c_init();
platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
omap_board_config = sdp3430_config;
omap_board_config_size = ARRAY_SIZE(sdp3430_config);
if (omap_rev() > OMAP3430_REV_ES1_0)
ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
else
@@ -495,6 +495,7 @@ static void __init omap_3430sdp_init(void)
omap_serial_init();
usb_musb_init();
board_smc91x_init();
enable_board_wakeup_source();
}
static void __init omap_3430sdp_map_io(void)

7
arch/arm/mach-omap2/board-4430sdp.c
Visa fil

@@ -39,7 +39,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
};
static struct omap_uart_config sdp4430_uart_config __initdata = {
.enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2),
.enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
};
static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -47,14 +47,13 @@ static struct omap_lcd_config sdp4430_lcd_config __initdata = {
};
static struct omap_board_config_kernel sdp4430_config[] __initdata = {
{ OMAP_TAG_UART, &sdp4430_uart_config },
{ OMAP_TAG_LCD, &sdp4430_lcd_config },
};
static void __init gic_init_irq(void)
{
gic_dist_init(0, IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
}
static void __init omap_4430sdp_init_irq(void)

25
arch/arm/mach-omap2/board-apollon.c
Visa fil

@@ -248,18 +248,6 @@ out:
clk_put(gpmc_fck);
}
static void __init omap_apollon_init_irq(void)
{
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
apollon_init_smc91x();
}
static struct omap_uart_config apollon_uart_config __initdata = {
.enabled_uarts = (1 << 0) | (0 << 1) | (0 << 2),
};
static struct omap_usb_config apollon_usb_config __initdata = {
.register_dev = 1,
.hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */
@@ -272,10 +260,19 @@ static struct omap_lcd_config apollon_lcd_config __initdata = {
};
static struct omap_board_config_kernel apollon_config[] = {
{ OMAP_TAG_UART, &apollon_uart_config },
{ OMAP_TAG_LCD, &apollon_lcd_config },
};
static void __init omap_apollon_init_irq(void)
{
omap_board_config = apollon_config;
omap_board_config_size = ARRAY_SIZE(apollon_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
apollon_init_smc91x();
}
static void __init apollon_led_init(void)
{
/* LED0 - AA10 */
@@ -324,8 +321,6 @@ static void __init omap_apollon_init(void)
* if not needed.
*/
platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
omap_board_config = apollon_config;
omap_board_config_size = ARRAY_SIZE(apollon_config);
omap_serial_init();
}

15
arch/arm/mach-omap2/board-generic.c
Visa fil

@@ -31,24 +31,19 @@
#include <mach/board.h>
#include <mach/common.h>
static struct omap_board_config_kernel generic_config[] = {
};
static void __init omap_generic_init_irq(void)
{
omap_board_config = generic_config;
omap_board_config_size = ARRAY_SIZE(generic_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
}
static struct omap_uart_config generic_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel generic_config[] = {
{ OMAP_TAG_UART, &generic_uart_config },
};
static void __init omap_generic_init(void)
{
omap_board_config = generic_config;
omap_board_config_size = ARRAY_SIZE(generic_config);
omap_serial_init();
}

25
arch/arm/mach-omap2/board-h4.c
Visa fil

@@ -268,18 +268,6 @@ static void __init h4_init_flash(void)
h4_flash_resource.end = base + SZ_64M - 1;
}
static void __init omap_h4_init_irq(void)
{
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
h4_init_flash();
}
static struct omap_uart_config h4_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_lcd_config h4_lcd_config __initdata = {
.ctrl_name = "internal",
};
@@ -318,10 +306,19 @@ static struct omap_usb_config h4_usb_config __initdata = {
};
static struct omap_board_config_kernel h4_config[] = {
{ OMAP_TAG_UART, &h4_uart_config },
{ OMAP_TAG_LCD, &h4_lcd_config },
};
static void __init omap_h4_init_irq(void)
{
omap_board_config = h4_config;
omap_board_config_size = ARRAY_SIZE(h4_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
h4_init_flash();
}
static struct at24_platform_data m24c01 = {
.byte_len = SZ_1K / 8,
.page_size = 16,
@@ -366,8 +363,6 @@ static void __init omap_h4_init(void)
ARRAY_SIZE(h4_i2c_board_info));
platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
omap_board_config = h4_config;
omap_board_config_size = ARRAY_SIZE(h4_config);
omap_usb_init(&h4_usb_config);
omap_serial_init();
}

25
arch/arm/mach-omap2/board-ldp.c
Visa fil

@@ -268,18 +268,6 @@ static inline void __init ldp_init_smsc911x(void)
gpio_direction_input(eth_gpio);
}
static void __init omap_ldp_init_irq(void)
{
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
ldp_init_smsc911x();
}
static struct omap_uart_config ldp_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct platform_device ldp_lcd_device = {
.name = "ldp_lcd",
.id = -1,
@@ -290,10 +278,19 @@ static struct omap_lcd_config ldp_lcd_config __initdata = {
};
static struct omap_board_config_kernel ldp_config[] __initdata = {
{ OMAP_TAG_UART, &ldp_uart_config },
{ OMAP_TAG_LCD, &ldp_lcd_config },
};
static void __init omap_ldp_init_irq(void)
{
omap_board_config = ldp_config;
omap_board_config_size = ARRAY_SIZE(ldp_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
ldp_init_smsc911x();
}
static struct twl4030_usb_data ldp_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
@@ -377,8 +374,6 @@ static void __init omap_ldp_init(void)
{
omap_i2c_init();
platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
omap_board_config = ldp_config;
omap_board_config_size = ARRAY_SIZE(ldp_config);
ts_gpio = 54;
ldp_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
spi_register_board_info(ldp_spi_board_info,

150
arch/arm/mach-omap2/board-n8x0.c Normal file
Visa fil

@@ -0,0 +1,150 @@
/*
* linux/arch/arm/mach-omap2/board-n8x0.c
*
* Copyright (C) 2005-2009 Nokia Corporation
* Author: Juha Yrjola <juha.yrjola@nokia.com>
*
* Modified from mach-omap2/board-generic.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/stddef.h>
#include <linux/spi/spi.h>
#include <linux/usb/musb.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/board.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/mcspi.h>
#include <mach/onenand.h>
#include <mach/serial.h>
static struct omap2_mcspi_device_config p54spi_mcspi_config = {
.turbo_mode = 0,
.single_channel = 1,
};
static struct spi_board_info n800_spi_board_info[] __initdata = {
{
.modalias = "p54spi",
.bus_num = 2,
.chip_select = 0,
.max_speed_hz = 48000000,
.controller_data = &p54spi_mcspi_config,
},
};
#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
static struct mtd_partition onenand_partitions[] = {
{
.name = "bootloader",
.offset = 0,
.size = 0x20000,
.mask_flags = MTD_WRITEABLE, /* Force read-only */
},
{
.name = "config",
.offset = MTDPART_OFS_APPEND,
.size = 0x60000,
},
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = 0x200000,
},
{
.name = "initfs",
.offset = MTDPART_OFS_APPEND,
.size = 0x400000,
},
{
.name = "rootfs",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct omap_onenand_platform_data board_onenand_data = {
.cs = 0,
.gpio_irq = 26,
.parts = onenand_partitions,
.nr_parts = ARRAY_SIZE(onenand_partitions),
.flags = ONENAND_SYNC_READ,
};
static void __init n8x0_onenand_init(void)
{
gpmc_onenand_init(&board_onenand_data);
}
#else
static void __init n8x0_onenand_init(void) {}
#endif
static void __init n8x0_map_io(void)
{
omap2_set_globals_242x();
omap2_map_common_io();
}
static void __init n8x0_init_irq(void)
{
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
}
static void __init n8x0_init_machine(void)
{
/* FIXME: add n810 spi devices */
spi_register_board_info(n800_spi_board_info,
ARRAY_SIZE(n800_spi_board_info));
omap_serial_init();
n8x0_onenand_init();
}
MACHINE_START(NOKIA_N800, "Nokia N800")
.phys_io = 0x48000000,
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.init_irq = n8x0_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
MACHINE_END
MACHINE_START(NOKIA_N810, "Nokia N810")
.phys_io = 0x48000000,
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.init_irq = n8x0_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
MACHINE_END
MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.phys_io = 0x48000000,
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = n8x0_map_io,
.init_irq = n8x0_init_irq,
.init_machine = n8x0_init_machine,
.timer = &omap_timer,
MACHINE_END

36
arch/arm/mach-omap2/board-omap3beagle.c
Visa fil

@@ -108,10 +108,6 @@ static struct platform_device omap3beagle_nand_device = {
#include "sdram-micron-mt46h32m32lf-6.h"
static struct omap_uart_config omap3_beagle_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct twl4030_hsmmc_info mmc[] = {
{
.mmc = 1,
@@ -249,11 +245,16 @@ static struct regulator_init_data beagle_vpll2 = {
.consumer_supplies = &beagle_vdvi_supply,
};
static struct twl4030_usb_data beagle_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_platform_data beagle_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.usb = &beagle_usb_data,
.gpio = &beagle_gpio_data,
.vmmc1 = &beagle_vmmc1,
.vsim = &beagle_vsim,
@@ -280,17 +281,6 @@ static int __init omap3_beagle_i2c_init(void)
return 0;
}
static void __init omap3_beagle_init_irq(void)
{
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
omap_gpio_init();
}
static struct gpio_led gpio_leds[] = {
{
.name = "beagleboard::usr0",
@@ -345,10 +335,22 @@ static struct platform_device keys_gpio = {
};
static struct omap_board_config_kernel omap3_beagle_config[] __initdata = {
{ OMAP_TAG_UART, &omap3_beagle_uart_config },
{ OMAP_TAG_LCD, &omap3_beagle_lcd_config },
};
static void __init omap3_beagle_init_irq(void)
{
omap_board_config = omap3_beagle_config;
omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
omap_gpio_init();
}
static struct platform_device *omap3_beagle_devices[] __initdata = {
&omap3_beagle_lcd_device,
&leds_gpio,
@@ -398,8 +400,6 @@ static void __init omap3_beagle_init(void)
omap3_beagle_i2c_init();
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
omap_board_config = omap3_beagle_config;
omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
omap_serial_init();
omap_cfg_reg(J25_34XX_GPIO170);

17
arch/arm/mach-omap2/board-omap3evm.c
Visa fil

@@ -92,10 +92,6 @@ static inline void __init omap3evm_init_smc911x(void)
gpio_direction_input(OMAP3EVM_ETHR_GPIO_IRQ);
}
static struct omap_uart_config omap3_evm_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct twl4030_hsmmc_info mmc[] = {
{
.mmc = 1,
@@ -278,19 +274,20 @@ struct spi_board_info omap3evm_spi_board_info[] = {
},
};
static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
{ OMAP_TAG_LCD, &omap3_evm_lcd_config },
};
static void __init omap3_evm_init_irq(void)
{
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
omap_init_irq();
omap_gpio_init();
omap3evm_init_smc911x();
}
static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
{ OMAP_TAG_UART, &omap3_evm_uart_config },
{ OMAP_TAG_LCD, &omap3_evm_lcd_config },
};
static struct platform_device *omap3_evm_devices[] __initdata = {
&omap3_evm_lcd_device,
&omap3evm_smc911x_device,
@@ -301,8 +298,6 @@ static void __init omap3_evm_init(void)
omap3_evm_i2c_init();
platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
omap_board_config = omap3_evm_config;
omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
spi_register_board_info(omap3evm_spi_board_info,
ARRAY_SIZE(omap3evm_spi_board_info));

25
arch/arm/mach-omap2/board-omap3pandora.c
Visa fil

@@ -213,10 +213,6 @@ static struct twl4030_hsmmc_info omap3pandora_mmc[] = {
{} /* Terminator */
};
static struct omap_uart_config omap3pandora_uart_config __initdata = {
.enabled_uarts = (1 << 2), /* UART3 */
};
static struct regulator_consumer_supply pandora_vmmc1_supply = {
.supply = "vmmc",
};
@@ -309,14 +305,6 @@ static int __init omap3pandora_i2c_init(void)
return 0;
}
static void __init omap3pandora_init_irq(void)
{
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
}
static void __init omap3pandora_ads7846_init(void)
{
int gpio = OMAP3_PANDORA_TS_GPIO;
@@ -376,10 +364,19 @@ static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
};
static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
{ OMAP_TAG_UART, &omap3pandora_uart_config },
{ OMAP_TAG_LCD, &omap3pandora_lcd_config },
};
static void __init omap3pandora_init_irq(void)
{
omap_board_config = omap3pandora_config;
omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
}
static struct platform_device *omap3pandora_devices[] __initdata = {
&omap3pandora_lcd_device,
&pandora_leds_gpio,
@@ -391,8 +388,6 @@ static void __init omap3pandora_init(void)
omap3pandora_i2c_init();
platform_add_devices(omap3pandora_devices,
ARRAY_SIZE(omap3pandora_devices));
omap_board_config = omap3pandora_config;
omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
omap_serial_init();
spi_register_board_info(omap3pandora_spi_board_info,
ARRAY_SIZE(omap3pandora_spi_board_info));

24
arch/arm/mach-omap2/board-overo.c
Visa fil

@@ -271,9 +271,6 @@ static void __init overo_flash_init(void)
printk(KERN_ERR "Unable to register NAND device\n");
}
}
static struct omap_uart_config overo_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct twl4030_hsmmc_info mmc[] = {
{
@@ -360,14 +357,6 @@ static int __init overo_i2c_init(void)
return 0;
}
static void __init overo_init_irq(void)
{
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
}
static struct platform_device overo_lcd_device = {
.name = "overo_lcd",
.id = -1,
@@ -378,10 +367,19 @@ static struct omap_lcd_config overo_lcd_config __initdata = {
};
static struct omap_board_config_kernel overo_config[] __initdata = {
{ OMAP_TAG_UART, &overo_uart_config },
{ OMAP_TAG_LCD, &overo_lcd_config },
};
static void __init overo_init_irq(void)
{
omap_board_config = overo_config;
omap_board_config_size = ARRAY_SIZE(overo_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
}
static struct platform_device *overo_devices[] __initdata = {
&overo_lcd_device,
};
@@ -390,8 +388,6 @@ static void __init overo_init(void)
{
overo_i2c_init();
platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
omap_board_config = overo_config;
omap_board_config_size = ARRAY_SIZE(overo_config);
omap_serial_init();
overo_flash_init();
usb_musb_init();

122
arch/arm/mach-omap2/board-rx51-peripherals.c
Visa fil

@@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-omap2/board-rx51-flash.c
* linux/arch/arm/mach-omap2/board-rx51-peripherals.c
*
* Copyright (C) 2008-2009 Nokia
*
@@ -282,7 +282,124 @@ static struct twl4030_usb_data rx51_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_platform_data rx51_twldata = {
static struct twl4030_ins sleep_on_seq[] __initdata = {
/*
* Turn off VDD1 and VDD2.
*/
{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_OFF), 4},
{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_OFF), 2},
/*
* And also turn off the OMAP3 PLLs and the sysclk output.
*/
{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_OFF), 3},
{MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_OFF), 3},
};
static struct twl4030_script sleep_on_script __initdata = {
.script = sleep_on_seq,
.size = ARRAY_SIZE(sleep_on_seq),
.flags = TWL4030_SLEEP_SCRIPT,
};
static struct twl4030_ins wakeup_seq[] __initdata = {
/*
* Reenable the OMAP3 PLLs.
* Wakeup VDD1 and VDD2.
* Reenable sysclk output.
*/
{MSG_SINGULAR(DEV_GRP_P1, 0x7, RES_STATE_ACTIVE), 0x30},
{MSG_SINGULAR(DEV_GRP_P1, 0xf, RES_STATE_ACTIVE), 0x30},
{MSG_SINGULAR(DEV_GRP_P1, 0x10, RES_STATE_ACTIVE), 0x37},
{MSG_SINGULAR(DEV_GRP_P1, 0x19, RES_STATE_ACTIVE), 3},
};
static struct twl4030_script wakeup_script __initdata = {
.script = wakeup_seq,
.size = ARRAY_SIZE(wakeup_seq),
.flags = TWL4030_WAKEUP12_SCRIPT,
};
static struct twl4030_ins wakeup_p3_seq[] __initdata = {
/*
* Wakeup VDD1 (dummy to be able to insert a delay)
* Enable CLKEN
*/
{MSG_SINGULAR(DEV_GRP_P1, 0x17, RES_STATE_ACTIVE), 3},
};
static struct twl4030_script wakeup_p3_script __initdata = {
.script = wakeup_p3_seq,
.size = ARRAY_SIZE(wakeup_p3_seq),
.flags = TWL4030_WAKEUP3_SCRIPT,
};
static struct twl4030_ins wrst_seq[] __initdata = {
/*
* Reset twl4030.
* Reset VDD1 regulator.
* Reset VDD2 regulator.
* Reset VPLL1 regulator.
* Enable sysclk output.
* Reenable twl4030.
*/
{MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_OFF), 2},
{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_ALL, 0, 1, RES_STATE_ACTIVE),
0x13},
{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 2, RES_STATE_WRST), 0x13},
{MSG_BROADCAST(DEV_GRP_NULL, RES_GRP_PP, 0, 3, RES_STATE_OFF), 0x13},
{MSG_SINGULAR(DEV_GRP_NULL, RES_VDD1, RES_STATE_WRST), 0x13},
{MSG_SINGULAR(DEV_GRP_NULL, RES_VDD2, RES_STATE_WRST), 0x13},
{MSG_SINGULAR(DEV_GRP_NULL, RES_VPLL1, RES_STATE_WRST), 0x35},
{MSG_SINGULAR(DEV_GRP_P1, RES_HFCLKOUT, RES_STATE_ACTIVE), 2},
{MSG_SINGULAR(DEV_GRP_NULL, RES_RESET, RES_STATE_ACTIVE), 2},
};
static struct twl4030_script wrst_script __initdata = {
.script = wrst_seq,
.size = ARRAY_SIZE(wrst_seq),
.flags = TWL4030_WRST_SCRIPT,
};
static struct twl4030_script *twl4030_scripts[] __initdata = {
/* wakeup12 script should be loaded before sleep script, otherwise a
board might hit retention before loading of wakeup script is
completed. This can cause boot failures depending on timing issues.
*/
&wakeup_script,
&sleep_on_script,
&wakeup_p3_script,
&wrst_script,
};
static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
{ .resource = RES_VINTANA1, .devgroup = -1, .type = -1, .type2 = 1 },
{ .resource = RES_VINTANA2, .devgroup = -1, .type = -1, .type2 = 1 },
{ .resource = RES_VINTDIG, .devgroup = -1, .type = -1, .type2 = 1 },
{ .resource = RES_VMMC1, .devgroup = -1, .type = -1, .type2 = 3},
{ .resource = RES_VMMC2, .devgroup = DEV_GRP_NULL, .type = -1,
.type2 = 3},
{ .resource = RES_VAUX1, .devgroup = -1, .type = -1, .type2 = 3},
{ .resource = RES_VAUX2, .devgroup = -1, .type = -1, .type2 = 3},
{ .resource = RES_VAUX3, .devgroup = -1, .type = -1, .type2 = 3},
{ .resource = RES_VAUX4, .devgroup = -1, .type = -1, .type2 = 3},
{ .resource = RES_VPLL2, .devgroup = -1, .type = -1, .type2 = 3},
{ .resource = RES_VDAC, .devgroup = -1, .type = -1, .type2 = 3},
{ .resource = RES_VSIM, .devgroup = DEV_GRP_NULL, .type = -1,
.type2 = 3},
{ .resource = RES_CLKEN, .devgroup = DEV_GRP_P3, .type = -1,
.type2 = 1 },
{ 0, 0},
};
static struct twl4030_power_data rx51_t2scripts_data __initdata = {
.scripts = twl4030_scripts,
.num = ARRAY_SIZE(twl4030_scripts),
.resource_config = twl4030_rconfig,
};
static struct twl4030_platform_data rx51_twldata __initdata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
@@ -291,6 +408,7 @@ static struct twl4030_platform_data rx51_twldata = {
.keypad = &rx51_kp_data,
.madc = &rx51_madc_data,
.usb = &rx51_usb_data,
.power = &rx51_t2scripts_data,
.vaux1 = &rx51_vaux1,
.vaux2 = &rx51_vaux2,

9
arch/arm/mach-omap2/board-rx51.c
Visa fil

@@ -31,10 +31,6 @@
#include <mach/gpmc.h>
#include <mach/usb.h>
static struct omap_uart_config rx51_uart_config = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_lcd_config rx51_lcd_config = {
.ctrl_name = "internal",
};
@@ -52,7 +48,6 @@ static struct omap_fbmem_config rx51_fbmem2_config = {
};
static struct omap_board_config_kernel rx51_config[] = {
{ OMAP_TAG_UART, &rx51_uart_config },
{ OMAP_TAG_FBMEM, &rx51_fbmem0_config },
{ OMAP_TAG_FBMEM, &rx51_fbmem1_config },
{ OMAP_TAG_FBMEM, &rx51_fbmem2_config },
@@ -61,6 +56,8 @@ static struct omap_board_config_kernel rx51_config[] = {
static void __init rx51_init_irq(void)
{
omap_board_config = rx51_config;
omap_board_config_size = ARRAY_SIZE(rx51_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
@@ -70,8 +67,6 @@ extern void __init rx51_peripherals_init(void);
static void __init rx51_init(void)
{
omap_board_config = rx51_config;
omap_board_config_size = ARRAY_SIZE(rx51_config);
omap_serial_init();
usb_musb_init();
rx51_peripherals_init();

11
arch/arm/mach-omap2/board-zoom-debugboard.c
Visa fil

@@ -12,6 +12,7 @@
#include <linux/gpio.h>
#include <linux/serial_8250.h>
#include <linux/smsc911x.h>
#include <linux/interrupt.h>
#include <mach/gpmc.h>
@@ -84,6 +85,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
.mapbase = 0x10000000,
.irq = OMAP_GPIO_IRQ(102),
.flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP|UPF_SHARE_IRQ,
.irqflags = IRQF_SHARED | IRQF_TRIGGER_RISING,
.iotype = UPIO_MEM,
.regshift = 1,
.uartclk = QUART_CLK,
@@ -94,7 +96,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
static struct platform_device zoom2_debugboard_serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.id = 3,
.dev = {
.platform_data = serial_platform_data,
},
@@ -127,6 +129,7 @@ static inline void __init zoom2_init_quaduart(void)
static inline int omap_zoom2_debugboard_detect(void)
{
int debug_board_detect = 0;
int ret = 1;
debug_board_detect = ZOOM2_SMSC911X_GPIO;
@@ -138,10 +141,10 @@ static inline int omap_zoom2_debugboard_detect(void)
gpio_direction_input(debug_board_detect);
if (!gpio_get_value(debug_board_detect)) {
gpio_free(debug_board_detect);
return 0;
ret = 0;
}
return 1;
gpio_free(debug_board_detect);
return ret;
}
static struct platform_device *zoom2_devices[] __initdata = {

218
arch/arm/mach-omap2/board-zoom2.c
Visa fil

@@ -12,36 +12,217 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/i2c/twl4030.h>
#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/common.h>
#include <mach/usb.h>
#include <mach/keypad.h>
#include "mmc-twl4030.h"
/* Zoom2 has Qwerty keyboard*/
static int zoom2_twl4030_keymap[] = {
KEY(0, 0, KEY_E),
KEY(1, 0, KEY_R),
KEY(2, 0, KEY_T),
KEY(3, 0, KEY_HOME),
KEY(6, 0, KEY_I),
KEY(7, 0, KEY_LEFTSHIFT),
KEY(0, 1, KEY_D),
KEY(1, 1, KEY_F),
KEY(2, 1, KEY_G),
KEY(3, 1, KEY_SEND),
KEY(6, 1, KEY_K),
KEY(7, 1, KEY_ENTER),
KEY(0, 2, KEY_X),
KEY(1, 2, KEY_C),
KEY(2, 2, KEY_V),
KEY(3, 2, KEY_END),
KEY(6, 2, KEY_DOT),
KEY(7, 2, KEY_CAPSLOCK),
KEY(0, 3, KEY_Z),
KEY(1, 3, KEY_KPPLUS),
KEY(2, 3, KEY_B),
KEY(3, 3, KEY_F1),
KEY(6, 3, KEY_O),
KEY(7, 3, KEY_SPACE),
KEY(0, 4, KEY_W),
KEY(1, 4, KEY_Y),
KEY(2, 4, KEY_U),
KEY(3, 4, KEY_F2),
KEY(4, 4, KEY_VOLUMEUP),
KEY(6, 4, KEY_L),
KEY(7, 4, KEY_LEFT),
KEY(0, 5, KEY_S),
KEY(1, 5, KEY_H),
KEY(2, 5, KEY_J),
KEY(3, 5, KEY_F3),
KEY(5, 5, KEY_VOLUMEDOWN),
KEY(6, 5, KEY_M),
KEY(4, 5, KEY_ENTER),
KEY(7, 5, KEY_RIGHT),
KEY(0, 6, KEY_Q),
KEY(1, 6, KEY_A),
KEY(2, 6, KEY_N),
KEY(3, 6, KEY_BACKSPACE),
KEY(6, 6, KEY_P),
KEY(7, 6, KEY_UP),
KEY(6, 7, KEY_SELECT),
KEY(7, 7, KEY_DOWN),
KEY(0, 7, KEY_PROG1), /*MACRO 1 <User defined> */
KEY(1, 7, KEY_PROG2), /*MACRO 2 <User defined> */
KEY(2, 7, KEY_PROG3), /*MACRO 3 <User defined> */
KEY(3, 7, KEY_PROG4), /*MACRO 4 <User defined> */
0
};
static struct twl4030_keypad_data zoom2_kp_twl4030_data = {
.rows = 8,
.cols = 8,
.keymap = zoom2_twl4030_keymap,
.keymapsize = ARRAY_SIZE(zoom2_twl4030_keymap),
.rep = 1,
};
static struct omap_board_config_kernel zoom2_config[] __initdata = {
};
static struct regulator_consumer_supply zoom2_vmmc1_supply = {
.supply = "vmmc",
};
static struct regulator_consumer_supply zoom2_vsim_supply = {
.supply = "vmmc_aux",
};
static struct regulator_consumer_supply zoom2_vmmc2_supply = {
.supply = "vmmc",
};
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data zoom2_vmmc1 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &zoom2_vmmc1_supply,
};
/* VMMC2 for MMC2 card */
static struct regulator_init_data zoom2_vmmc2 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 1850000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &zoom2_vmmc2_supply,
};
/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
static struct regulator_init_data zoom2_vsim = {
.constraints = {
.min_uV = 1800000,
.max_uV = 3000000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &zoom2_vsim_supply,
};
static struct twl4030_hsmmc_info mmc[] __initdata = {
{
.mmc = 1,
.wires = 4,
.gpio_wp = -EINVAL,
},
{
.mmc = 2,
.wires = 4,
.gpio_wp = -EINVAL,
},
{} /* Terminator */
};
static int zoom2_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
/* gpio + 0 is "mmc0_cd" (input/IRQ),
* gpio + 1 is "mmc1_cd" (input/IRQ)
*/
mmc[0].gpio_cd = gpio + 0;
mmc[1].gpio_cd = gpio + 1;
twl4030_mmc_init(mmc);
/* link regulators to MMC adapters ... we "know" the
* regulators will be set up only *after* we return.
*/
zoom2_vmmc1_supply.dev = mmc[0].dev;
zoom2_vsim_supply.dev = mmc[0].dev;
zoom2_vmmc2_supply.dev = mmc[1].dev;
return 0;
}
static int zoom2_batt_table[] = {
/* 0 C*/
30800, 29500, 28300, 27100,
26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
4040, 3910, 3790, 3670, 3550
};
static struct twl4030_bci_platform_data zoom2_bci_data = {
.battery_tmp_tbl = zoom2_batt_table,
.tblsize = ARRAY_SIZE(zoom2_batt_table),
};
static struct twl4030_usb_data zoom2_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static void __init omap_zoom2_init_irq(void)
{
omap_board_config = zoom2_config;
omap_board_config_size = ARRAY_SIZE(zoom2_config);
omap2_init_common_hw(NULL, NULL);
omap_init_irq();
omap_gpio_init();
}
static struct omap_uart_config zoom2_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel zoom2_config[] __initdata = {
{ OMAP_TAG_UART, &zoom2_uart_config },
};
static struct twl4030_gpio_platform_data zoom2_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
.irq_end = TWL4030_GPIO_IRQ_END,
.setup = zoom2_twl_gpio_setup,
};
static struct twl4030_madc_platform_data zoom2_madc_data = {
.irq_line = 1,
};
static struct twl4030_platform_data zoom2_twldata = {
@@ -49,7 +230,15 @@ static struct twl4030_platform_data zoom2_twldata = {
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.bci = &zoom2_bci_data,
.madc = &zoom2_madc_data,
.usb = &zoom2_usb_data,
.gpio = &zoom2_gpio_data,
.keypad = &zoom2_kp_twl4030_data,
.vmmc1 = &zoom2_vmmc1,
.vmmc2 = &zoom2_vmmc2,
.vsim = &zoom2_vsim,
};
static struct i2c_board_info __initdata zoom2_i2c_boardinfo[] = {
@@ -70,26 +259,13 @@ static int __init omap_i2c_init(void)
return 0;
}
static struct twl4030_hsmmc_info mmc[] __initdata = {
{
.mmc = 1,
.wires = 4,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
},
{} /* Terminator */
};
extern int __init omap_zoom2_debugboard_init(void);
static void __init omap_zoom2_init(void)
{
omap_i2c_init();
omap_board_config = zoom2_config;
omap_board_config_size = ARRAY_SIZE(zoom2_config);
omap_serial_init();
omap_zoom2_debugboard_init();
twl4030_mmc_init(mmc);
usb_musb_init();
}

2
arch/arm/mach-omap2/clock.c
Visa fil

@@ -1043,5 +1043,7 @@ void omap2_clk_disable_unused(struct clk *clk)
omap2_clk_disable(clk);
} else
_omap2_clk_disable(clk);
if (clk->clkdm != NULL)
pwrdm_clkdm_state_switch(clk->clkdm);
}
#endif

17
arch/arm/mach-omap2/clock34xx.c
Visa fil

@@ -27,6 +27,7 @@
#include <linux/limits.h>
#include <linux/bitops.h>
#include <mach/cpu.h>
#include <mach/clock.h>
#include <mach/sram.h>
#include <asm/div64.h>
@@ -1067,17 +1068,17 @@ static int __init omap2_clk_arch_init(void)
return -EINVAL;
/* REVISIT: not yet ready for 343x */
#if 0
if (clk_set_rate(&virt_prcm_set, mpurate))
printk(KERN_ERR "Could not find matching MPU rate\n");
#endif
if (clk_set_rate(&dpll1_ck, mpurate))
printk(KERN_ERR "*** Unable to set MPU rate\n");
recalculate_root_clocks();
printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
"%ld.%01ld/%ld/%ld MHz\n",
(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
(core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
(osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
(core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
calibrate_delay();
return 0;
}
@@ -1136,7 +1137,7 @@ int __init omap2_clk_init(void)
recalculate_root_clocks();
printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
"%ld.%01ld/%ld/%ld MHz\n",
(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
(core_ck.rate / 1000000), (arm_fck.rate / 1000000));

21
arch/arm/mach-omap2/clock34xx.h
Visa fil

@@ -1020,6 +1020,7 @@ static struct clk arm_fck = {
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
.clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
.clksel = arm_fck_clksel,
.clkdm_name = "mpu_clkdm",
.recalc = &omap2_clksel_recalc,
};
@@ -1155,7 +1156,6 @@ static struct clk gfx_cg1_ck = {
.name = "gfx_cg1_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &gfx_l3_fck, /* REVISIT: correct? */
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
.clkdm_name = "gfx_3430es1_clkdm",
@@ -1166,7 +1166,6 @@ static struct clk gfx_cg2_ck = {
.name = "gfx_cg2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &gfx_l3_fck, /* REVISIT: correct? */
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
.clkdm_name = "gfx_3430es1_clkdm",
@@ -1210,7 +1209,6 @@ static struct clk sgx_ick = {
.name = "sgx_ick",
.ops = &clkops_omap2_dflt_wait,
.parent = &l3_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
.clkdm_name = "sgx_clkdm",
@@ -1223,7 +1221,6 @@ static struct clk d2d_26m_fck = {
.name = "d2d_26m_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
.clkdm_name = "d2d_clkdm",
@@ -1234,7 +1231,6 @@ static struct clk modem_fck = {
.name = "modem_fck",
.ops = &clkops_omap2_dflt_wait,
.parent = &sys_ck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MODEM_SHIFT,
.clkdm_name = "d2d_clkdm",
@@ -1622,7 +1618,6 @@ static struct clk core_l3_ick = {
.name = "core_l3_ick",
.ops = &clkops_null,
.parent = &l3_ick,
.init = &omap2_init_clk_clkdm,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc,
};
@@ -1691,7 +1686,6 @@ static struct clk core_l4_ick = {
.name = "core_l4_ick",
.ops = &clkops_null,
.parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
@@ -2089,7 +2083,6 @@ static struct clk dss_tv_fck = {
.name = "dss_tv_fck",
.ops = &clkops_omap2_dflt,
.parent = &omap_54m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.clkdm_name = "dss_clkdm",
@@ -2100,7 +2093,6 @@ static struct clk dss_96m_fck = {
.name = "dss_96m_fck",
.ops = &clkops_omap2_dflt,
.parent = &omap_96m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.clkdm_name = "dss_clkdm",
@@ -2111,7 +2103,6 @@ static struct clk dss2_alwon_fck = {
.name = "dss2_alwon_fck",
.ops = &clkops_omap2_dflt,
.parent = &sys_ck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
.clkdm_name = "dss_clkdm",
@@ -2123,7 +2114,6 @@ static struct clk dss_ick_3430es1 = {
.name = "dss_ick",
.ops = &clkops_omap2_dflt,
.parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.clkdm_name = "dss_clkdm",
@@ -2135,7 +2125,6 @@ static struct clk dss_ick_3430es2 = {
.name = "dss_ick",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.clkdm_name = "dss_clkdm",
@@ -2159,7 +2148,6 @@ static struct clk cam_ick = {
.name = "cam_ick",
.ops = &clkops_omap2_dflt,
.parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.clkdm_name = "cam_clkdm",
@@ -2170,7 +2158,6 @@ static struct clk csi2_96m_fck = {
.name = "csi2_96m_fck",
.ops = &clkops_omap2_dflt,
.parent = &core_96m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CSI2_SHIFT,
.clkdm_name = "cam_clkdm",
@@ -2183,7 +2170,6 @@ static struct clk usbhost_120m_fck = {
.name = "usbhost_120m_fck",
.ops = &clkops_omap2_dflt,
.parent = &dpll5_m2_ck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
.clkdm_name = "usbhost_clkdm",
@@ -2194,7 +2180,6 @@ static struct clk usbhost_48m_fck = {
.name = "usbhost_48m_fck",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &omap_48m_fck,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.clkdm_name = "usbhost_clkdm",
@@ -2206,7 +2191,6 @@ static struct clk usbhost_ick = {
.name = "usbhost_ick",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.clkdm_name = "usbhost_clkdm",
@@ -2268,7 +2252,6 @@ static struct clk gpt1_fck = {
static struct clk wkup_32k_fck = {
.name = "wkup_32k_fck",
.ops = &clkops_null,
.init = &omap2_init_clk_clkdm,
.parent = &omap_32k_fck,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
@@ -2383,7 +2366,6 @@ static struct clk per_96m_fck = {
.name = "per_96m_fck",
.ops = &clkops_null,
.parent = &omap_96m_alwon_fck,
.init = &omap2_init_clk_clkdm,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};
@@ -2392,7 +2374,6 @@ static struct clk per_48m_fck = {
.name = "per_48m_fck",
.ops = &clkops_null,
.parent = &omap_48m_fck,
.init = &omap2_init_clk_clkdm,
.clkdm_name = "per_clkdm",
.recalc = &followparent_recalc,
};

10
arch/arm/mach-omap2/clockdomain.c
Visa fil

@@ -299,7 +299,8 @@ struct clockdomain *clkdm_lookup(const char *name)
* anything else to indicate failure; or -EINVAL if the function pointer
* is null.
*/
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm))
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
void *user)
{
struct clockdomain *clkdm;
int ret = 0;
@@ -309,7 +310,7 @@ int clkdm_for_each(int (*fn)(struct clockdomain *clkdm))
mutex_lock(&clkdm_mutex);
list_for_each_entry(clkdm, &clkdm_list, node) {
ret = (*fn)(clkdm);
ret = (*fn)(clkdm, user);
if (ret)
break;
}
@@ -484,6 +485,8 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
v << __ffs(clkdm->clktrctrl_mask),
clkdm->pwrdm.ptr->prcm_offs,
CM_CLKSTCTRL);
pwrdm_clkdm_state_switch(clkdm);
}
/**
@@ -572,6 +575,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
omap2_clkdm_wakeup(clkdm);
pwrdm_wait_transition(clkdm->pwrdm.ptr);
pwrdm_clkdm_state_switch(clkdm);
return 0;
}
@@ -624,6 +628,8 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
else
omap2_clkdm_sleep(clkdm);
pwrdm_clkdm_state_switch(clkdm);
return 0;
}

70
arch/arm/mach-omap2/cm.c Normal file
Visa fil

@@ -0,0 +1,70 @@
/*
* OMAP2/3 CM module functions
*
* Copyright (C) 2009 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <asm/atomic.h>
#include "cm.h"
#include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h"
/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */
#define MAX_MODULE_READY_TIME 20000
static const u8 cm_idlest_offs[] = {
CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
};
/**
* omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
* @prcm_mod: PRCM module offset
* @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
* @idlest_shift: shift of the bit in the CM_IDLEST* register to check
*
* XXX document
*/
int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
{
int ena = 0, i = 0;
u8 cm_idlest_reg;
u32 mask;
if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
return -EINVAL;
cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
if (cpu_is_omap24xx())
ena = idlest_shift;
else if (cpu_is_omap34xx())
ena = 0;
else
BUG();
mask = 1 << idlest_shift;
/* XXX should be OMAP2 CM */
while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) &&
(i++ < MAX_MODULE_READY_TIME))
udelay(1);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}

10
arch/arm/mach-omap2/cm.h
Visa fil

@@ -17,11 +17,11 @@
#include "prcm-common.h"
#define OMAP2420_CM_REGADDR(module, reg) \
IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
#define OMAP2430_CM_REGADDR(module, reg) \
IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
#define OMAP34XX_CM_REGADDR(module, reg) \
IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
/*
* Architecture-specific global CM registers
@@ -98,6 +98,10 @@ extern u32 cm_read_mod_reg(s16 module, u16 idx);
extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
u8 idlest_shift);
extern int omap4_cm_wait_module_ready(u32 prcm_mod, u8 prcm_dev_offs);
static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
return cm_rmw_mod_reg_bits(bits, bits, module, idx);

68
arch/arm/mach-omap2/cm4xxx.c Normal file
Visa fil

@@ -0,0 +1,68 @@
/*
* OMAP4 CM module functions
*
* Copyright (C) 2009 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <asm/atomic.h>
#include "cm.h"
#include "cm-regbits-4xxx.h"
/* XXX move this to cm.h */
/* MAX_MODULE_READY_TIME: max milliseconds for module to leave idle */
#define MAX_MODULE_READY_TIME 20000
/*
* OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK: isolates the IDLEST field in the
* CM_CLKCTRL register.
*/
#define OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK (0x2 << 16)
/*
* OMAP4 prcm_mod u32 fields contain packed data: the CM ID in bit 16 and
* the PRCM module offset address (from the CM module base) in bits 15-0.
*/
#define OMAP4_PRCM_MOD_CM_ID_SHIFT 16
#define OMAP4_PRCM_MOD_OFFS_MASK 0xffff
/**
* omap4_cm_wait_idlest_ready - wait for a module to leave idle or standby
* @prcm_mod: PRCM module offset (XXX example)
* @prcm_dev_offs: PRCM device offset (e.g. MCASP XXX example)
*
* XXX document
*/
int omap4_cm_wait_idlest_ready(u32 prcm_mod, u8 prcm_dev_offs)
{
int i = 0;
u8 cm_id;
u16 prcm_mod_offs;
u32 mask = OMAP4_PRCM_CM_CLKCTRL_IDLEST_MASK;
cm_id = prcm_mod >> OMAP4_PRCM_MOD_CM_ID_SHIFT;
prcm_mod_offs = prcm_mod & OMAP4_PRCM_MOD_OFFS_MASK;
while (((omap4_cm_read_mod_reg(cm_id, prcm_mod_offs, prcm_dev_offs,
OMAP4_CM_CLKCTRL_DREG) & mask) != 0) &&
(i++ < MAX_MODULE_READY_TIME))
udelay(1);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}

41
arch/arm/mach-omap2/devices.c
Visa fil

@@ -513,6 +513,47 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
}
}
if (cpu_is_omap3430()) {
if (controller_nr == 0) {
omap_cfg_reg(N28_3430_MMC1_CLK);
omap_cfg_reg(M27_3430_MMC1_CMD);
omap_cfg_reg(N27_3430_MMC1_DAT0);
if (mmc_controller->slots[0].wires == 4 ||
mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(N26_3430_MMC1_DAT1);
omap_cfg_reg(N25_3430_MMC1_DAT2);
omap_cfg_reg(P28_3430_MMC1_DAT3);
}
if (mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(P27_3430_MMC1_DAT4);
omap_cfg_reg(P26_3430_MMC1_DAT5);
omap_cfg_reg(R27_3430_MMC1_DAT6);
omap_cfg_reg(R25_3430_MMC1_DAT7);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_cfg_reg(AE2_3430_MMC2_CLK);
omap_cfg_reg(AG5_3430_MMC2_CMD);
omap_cfg_reg(AH5_3430_MMC2_DAT0);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
* in the board-*.c files
*/
if (mmc_controller->slots[0].wires == 4 ||
mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(AH4_3430_MMC2_DAT1);
omap_cfg_reg(AG4_3430_MMC2_DAT2);
omap_cfg_reg(AF4_3430_MMC2_DAT3);
}
}
/*
* For MMC3 the pins need to be muxed in the board-*.c files
*/
}
}
void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,

23
arch/arm/mach-omap2/io.c
Visa fil

@@ -32,17 +32,23 @@
#include <mach/sram.h>
#include <mach/sdrc.h>
#include <mach/gpmc.h>
#include <mach/serial.h>
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
#include "clock.h"
#include <mach/omap-pm.h>
#include <mach/powerdomain.h>
#include "powerdomains.h"
#include <mach/clockdomain.h>
#include "clockdomains.h"
#endif
#include <mach/omap_hwmod.h>
#include "omap_hwmod_2420.h"
#include "omap_hwmod_2430.h"
#include "omap_hwmod_34xx.h"
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
@@ -279,11 +285,26 @@ static int __init _omap2_init_reprogram_sdrc(void)
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
struct omap_hwmod **hwmods = NULL;
if (cpu_is_omap2420())
hwmods = omap2420_hwmods;
else if (cpu_is_omap2430())
hwmods = omap2430_hwmods;
else if (cpu_is_omap34xx())
hwmods = omap34xx_hwmods;
omap_hwmod_init(hwmods);
omap2_mux_init();
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
/* The OPP tables have to be registered before a clk init */
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init();
omap_serial_early_init();
omap_hwmod_late_init();
omap_pm_if_init();
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
#endif

17
arch/arm/mach-omap2/iommu2.c
Visa fil

@@ -217,10 +217,19 @@ static ssize_t omap2_dump_cr(struct iommu *obj, struct cr_regs *cr, char *buf)
}
#define pr_reg(name) \
p += sprintf(p, "%20s: %08x\n", \
__stringify(name), iommu_read_reg(obj, MMU_##name));
do { \
ssize_t bytes; \
const char *str = "%20s: %08x\n"; \
const int maxcol = 32; \
bytes = snprintf(p, maxcol, str, __stringify(name), \
iommu_read_reg(obj, MMU_##name)); \
p += bytes; \
len -= bytes; \
if (len < maxcol) \
goto out; \
} while (0)
static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len)
{
char *p = buf;
@@ -242,7 +251,7 @@ static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf)
pr_reg(READ_CAM);
pr_reg(READ_RAM);
pr_reg(EMU_FAULT_AD);
out:
return p - buf;
}

46
arch/arm/mach-omap2/mcbsp.c
Visa fil

@@ -128,6 +128,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.buffer_size = 0x6F,
},
{
.phys_base = OMAP34XX_MCBSP2_BASE,
@@ -136,6 +137,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.buffer_size = 0x3FF,
},
{
.phys_base = OMAP34XX_MCBSP3_BASE,
@@ -144,6 +146,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.buffer_size = 0x6F,
},
{
.phys_base = OMAP34XX_MCBSP4_BASE,
@@ -152,6 +155,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.buffer_size = 0x6F,
},
{
.phys_base = OMAP34XX_MCBSP5_BASE,
@@ -160,6 +164,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.buffer_size = 0x6F,
},
};
#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
@@ -168,6 +173,42 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
#define OMAP34XX_MCBSP_PDATA_SZ 0
#endif
static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
{
.phys_base = OMAP44XX_MCBSP1_BASE,
.dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
.dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
.ops = &omap2_mcbsp_ops,
},
{
.phys_base = OMAP44XX_MCBSP2_BASE,
.dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
.dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
.ops = &omap2_mcbsp_ops,
},
{
.phys_base = OMAP44XX_MCBSP3_BASE,
.dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
.dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
.ops = &omap2_mcbsp_ops,
},
{
.phys_base = OMAP44XX_MCBSP4_BASE,
.dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
.dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
.ops = &omap2_mcbsp_ops,
},
};
#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
static int __init omap2_mcbsp_init(void)
{
if (cpu_is_omap2420())
@@ -176,6 +217,8 @@ static int __init omap2_mcbsp_init(void)
omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
if (cpu_is_omap34xx())
omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
if (cpu_is_omap44xx())
omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
GFP_KERNEL);
@@ -191,6 +234,9 @@ static int __init omap2_mcbsp_init(void)
if (cpu_is_omap34xx())
omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
OMAP34XX_MCBSP_PDATA_SZ);
if (cpu_is_omap44xx())
omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
OMAP44XX_MCBSP_PDATA_SZ);
return omap_mcbsp_init();
}

55
arch/arm/mach-omap2/mux.c
Visa fil

@@ -492,6 +492,61 @@ MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
/* MMC1 */
MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
/* MMC2 */
MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
/* MMC3 */
MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
/* SYS_NIRQ T2 INT1 */
MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0,
OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP |
OMAP34XX_MUX_MODE0)
};
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)

2
arch/arm/mach-omap2/omap-smp.c
Visa fil

@@ -54,7 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* for us: do so
*/
gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
/*
* Synchronise with the boot thread.

1554
arch/arm/mach-omap2/omap_hwmod.c Normal file
Visa fil

Filskillnaden har hållits tillbaka eftersom den är för stor Load Diff

141
arch/arm/mach-omap2/omap_hwmod_2420.h Normal file
Visa fil

@@ -0,0 +1,141 @@
/*
* omap_hwmod_2420.h - hardware modules present on the OMAP2420 chips
*
* Copyright (C) 2009 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* XXX handle crossbar/shared link difference for L3?
*
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2420_H
#ifdef CONFIG_ARCH_OMAP2420
#include <mach/omap_hwmod.h>
#include <mach/irqs.h>
#include <mach/cpu.h>
#include <mach/dma.h>
#include "prm-regbits-24xx.h"
static struct omap_hwmod omap2420_mpu_hwmod;
static struct omap_hwmod omap2420_l3_hwmod;
static struct omap_hwmod omap2420_l4_core_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2420_l3__l4_core = {
.master = &omap2420_l3_hwmod,
.slave = &omap2420_l4_core_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* MPU -> L3 interface */
static struct omap_hwmod_ocp_if omap2420_mpu__l3 = {
.master = &omap2420_mpu_hwmod,
.slave = &omap2420_l3_hwmod,
.user = OCP_USER_MPU,
};
/* Slave interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2420_l3_slaves[] = {
&omap2420_mpu__l3,
};
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2420_l3_masters[] = {
&omap2420_l3__l4_core,
};
/* L3 */
static struct omap_hwmod omap2420_l3_hwmod = {
.name = "l3_hwmod",
.masters = omap2420_l3_masters,
.masters_cnt = ARRAY_SIZE(omap2420_l3_masters),
.slaves = omap2420_l3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
static struct omap_hwmod omap2420_l4_wkup_hwmod;
/* L4_CORE -> L4_WKUP interface */
static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_l4_wkup_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
&omap2420_l3__l4_core,
};
/* Master interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
&omap2420_l4_core__l4_wkup,
};
/* L4 CORE */
static struct omap_hwmod omap2420_l4_core_hwmod = {
.name = "l4_core_hwmod",
.masters = omap2420_l4_core_masters,
.masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
.slaves = omap2420_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* Slave interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
&omap2420_l4_core__l4_wkup,
};
/* Master interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
};
/* L4 WKUP */
static struct omap_hwmod omap2420_l4_wkup_hwmod = {
.name = "l4_wkup_hwmod",
.masters = omap2420_l4_wkup_masters,
.masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
.slaves = omap2420_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* Master interfaces on the MPU device */
static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
&omap2420_mpu__l3,
};
/* MPU */
static struct omap_hwmod omap2420_mpu_hwmod = {
.name = "mpu_hwmod",
.clkdev_dev_id = NULL,
.clkdev_con_id = "mpu_ck",
.masters = omap2420_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
&omap2420_l3_hwmod,
&omap2420_l4_core_hwmod,
&omap2420_l4_wkup_hwmod,
&omap2420_mpu_hwmod,
NULL,
};
#else
# define omap2420_hwmods 0
#endif
#endif

143
arch/arm/mach-omap2/omap_hwmod_2430.h Normal file
Visa fil

@@ -0,0 +1,143 @@
/*
* omap_hwmod_2430.h - hardware modules present on the OMAP2430 chips
*
* Copyright (C) 2009 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* XXX handle crossbar/shared link difference for L3?
*
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD2430_H
#ifdef CONFIG_ARCH_OMAP2430
#include <mach/omap_hwmod.h>
#include <mach/irqs.h>
#include <mach/cpu.h>
#include <mach/dma.h>
#include "prm-regbits-24xx.h"
static struct omap_hwmod omap2430_mpu_hwmod;
static struct omap_hwmod omap2430_l3_hwmod;
static struct omap_hwmod omap2430_l4_core_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2430_l3__l4_core = {
.master = &omap2430_l3_hwmod,
.slave = &omap2430_l4_core_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* MPU -> L3 interface */
static struct omap_hwmod_ocp_if omap2430_mpu__l3 = {
.master = &omap2430_mpu_hwmod,
.slave = &omap2430_l3_hwmod,
.user = OCP_USER_MPU,
};
/* Slave interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2430_l3_slaves[] = {
&omap2430_mpu__l3,
};
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap2430_l3_masters[] = {
&omap2430_l3__l4_core,
};
/* L3 */
static struct omap_hwmod omap2430_l3_hwmod = {
.name = "l3_hwmod",
.masters = omap2430_l3_masters,
.masters_cnt = ARRAY_SIZE(omap2430_l3_masters),
.slaves = omap2430_l3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
static struct omap_hwmod omap2430_l4_wkup_hwmod;
static struct omap_hwmod omap2430_mmc1_hwmod;
static struct omap_hwmod omap2430_mmc2_hwmod;
/* L4_CORE -> L4_WKUP interface */
static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_l4_wkup_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
&omap2430_l3__l4_core,
};
/* Master interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
&omap2430_l4_core__l4_wkup,
};
/* L4 CORE */
static struct omap_hwmod omap2430_l4_core_hwmod = {
.name = "l4_core_hwmod",
.masters = omap2430_l4_core_masters,
.masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
.slaves = omap2430_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* Slave interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
&omap2430_l4_core__l4_wkup,
};
/* Master interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
};
/* L4 WKUP */
static struct omap_hwmod omap2430_l4_wkup_hwmod = {
.name = "l4_wkup_hwmod",
.masters = omap2430_l4_wkup_masters,
.masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
.slaves = omap2430_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* Master interfaces on the MPU device */
static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
&omap2430_mpu__l3,
};
/* MPU */
static struct omap_hwmod omap2430_mpu_hwmod = {
.name = "mpu_hwmod",
.clkdev_dev_id = NULL,
.clkdev_con_id = "mpu_ck",
.masters = omap2430_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
static __initdata struct omap_hwmod *omap2430_hwmods[] = {
&omap2430_l3_hwmod,
&omap2430_l4_core_hwmod,
&omap2430_l4_wkup_hwmod,
&omap2430_mpu_hwmod,
NULL,
};
#else
# define omap2430_hwmods 0
#endif
#endif

168
arch/arm/mach-omap2/omap_hwmod_34xx.h Normal file
Visa fil

@@ -0,0 +1,168 @@
/*
* omap_hwmod_34xx.h - hardware modules present on the OMAP34xx chips
*
* Copyright (C) 2009 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H
#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD34XX_H
#ifdef CONFIG_ARCH_OMAP34XX
#include <mach/omap_hwmod.h>
#include <mach/irqs.h>
#include <mach/cpu.h>
#include <mach/dma.h>
#include "prm-regbits-34xx.h"
static struct omap_hwmod omap34xx_mpu_hwmod;
static struct omap_hwmod omap34xx_l3_hwmod;
static struct omap_hwmod omap34xx_l4_core_hwmod;
static struct omap_hwmod omap34xx_l4_per_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap34xx_l3__l4_core = {
.master = &omap34xx_l3_hwmod,
.slave = &omap34xx_l4_core_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L3 -> L4_PER interface */
static struct omap_hwmod_ocp_if omap34xx_l3__l4_per = {
.master = &omap34xx_l3_hwmod,
.slave = &omap34xx_l4_per_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* MPU -> L3 interface */
static struct omap_hwmod_ocp_if omap34xx_mpu__l3 = {
.master = &omap34xx_mpu_hwmod,
.slave = &omap34xx_l3_hwmod,
.user = OCP_USER_MPU,
};
/* Slave interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap34xx_l3_slaves[] = {
&omap34xx_mpu__l3,
};
/* Master interfaces on the L3 interconnect */
static struct omap_hwmod_ocp_if *omap34xx_l3_masters[] = {
&omap34xx_l3__l4_core,
&omap34xx_l3__l4_per,
};
/* L3 */
static struct omap_hwmod omap34xx_l3_hwmod = {
.name = "l3_hwmod",
.masters = omap34xx_l3_masters,
.masters_cnt = ARRAY_SIZE(omap34xx_l3_masters),
.slaves = omap34xx_l3_slaves,
.slaves_cnt = ARRAY_SIZE(omap34xx_l3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
static struct omap_hwmod omap34xx_l4_wkup_hwmod;
/* L4_CORE -> L4_WKUP interface */
static struct omap_hwmod_ocp_if omap34xx_l4_core__l4_wkup = {
.master = &omap34xx_l4_core_hwmod,
.slave = &omap34xx_l4_wkup_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* Slave interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap34xx_l4_core_slaves[] = {
&omap34xx_l3__l4_core,
};
/* Master interfaces on the L4_CORE interconnect */
static struct omap_hwmod_ocp_if *omap34xx_l4_core_masters[] = {
&omap34xx_l4_core__l4_wkup,
};
/* L4 CORE */
static struct omap_hwmod omap34xx_l4_core_hwmod = {
.name = "l4_core_hwmod",
.masters = omap34xx_l4_core_masters,
.masters_cnt = ARRAY_SIZE(omap34xx_l4_core_masters),
.slaves = omap34xx_l4_core_slaves,
.slaves_cnt = ARRAY_SIZE(omap34xx_l4_core_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* Slave interfaces on the L4_PER interconnect */
static struct omap_hwmod_ocp_if *omap34xx_l4_per_slaves[] = {
&omap34xx_l3__l4_per,
};
/* Master interfaces on the L4_PER interconnect */
static struct omap_hwmod_ocp_if *omap34xx_l4_per_masters[] = {
};
/* L4 PER */
static struct omap_hwmod omap34xx_l4_per_hwmod = {
.name = "l4_per_hwmod",
.masters = omap34xx_l4_per_masters,
.masters_cnt = ARRAY_SIZE(omap34xx_l4_per_masters),
.slaves = omap34xx_l4_per_slaves,
.slaves_cnt = ARRAY_SIZE(omap34xx_l4_per_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* Slave interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_slaves[] = {
&omap34xx_l4_core__l4_wkup,
};
/* Master interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *omap34xx_l4_wkup_masters[] = {
};
/* L4 WKUP */
static struct omap_hwmod omap34xx_l4_wkup_hwmod = {
.name = "l4_wkup_hwmod",
.masters = omap34xx_l4_wkup_masters,
.masters_cnt = ARRAY_SIZE(omap34xx_l4_wkup_masters),
.slaves = omap34xx_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap34xx_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
};
/* Master interfaces on the MPU device */
static struct omap_hwmod_ocp_if *omap34xx_mpu_masters[] = {
&omap34xx_mpu__l3,
};
/* MPU */
static struct omap_hwmod omap34xx_mpu_hwmod = {
.name = "mpu_hwmod",
.clkdev_dev_id = NULL,
.clkdev_con_id = "arm_fck",
.masters = omap34xx_mpu_masters,
.masters_cnt = ARRAY_SIZE(omap34xx_mpu_masters),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
&omap34xx_l3_hwmod,
&omap34xx_l4_core_hwmod,
&omap34xx_l4_per_hwmod,
&omap34xx_l4_wkup_hwmod,
&omap34xx_mpu_hwmod,
NULL,
};
#else
# define omap34xx_hwmods 0
#endif
#endif

431
arch/arm/mach-omap2/pm-debug.c
Visa fil

@@ -20,13 +20,16 @@
*/
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/sched.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <mach/clock.h>
#include <mach/board.h>
#include <mach/powerdomain.h>
#include <mach/clockdomain.h>
#include "prm.h"
#include "cm.h"
@@ -48,7 +51,9 @@ int omap2_pm_debug;
regs[reg_count++].val = __raw_readl(reg)
#define DUMP_INTC_REG(reg, off) \
regs[reg_count].name = #reg; \
regs[reg_count++].val = __raw_readl(IO_ADDRESS(0x480fe000 + (off)))
regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off)))
static int __init pm_dbg_init(void);
void omap2_pm_dump(int mode, int resume, unsigned int us)
{
@@ -150,3 +155,425 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
for (i = 0; i < reg_count; i++)
printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
}
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
static void pm_dbg_regset_store(u32 *ptr);
struct dentry *pm_dbg_dir;
static int pm_dbg_init_done;
enum {
DEBUG_FILE_COUNTERS = 0,
DEBUG_FILE_TIMERS,
};
struct pm_module_def {
char name[8]; /* Name of the module */
short type; /* CM or PRM */
unsigned short offset;
int low; /* First register address on this module */
int high; /* Last register address on this module */
};
#define MOD_CM 0
#define MOD_PRM 1
static const struct pm_module_def *pm_dbg_reg_modules;
static const struct pm_module_def omap3_pm_reg_modules[] = {
{ "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
{ "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
{ "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
{ "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
{ "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
{ "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
{ "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
{ "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
{ "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
{ "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
{ "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
{ "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
{ "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
{ "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
{ "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
{ "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
{ "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
{ "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
{ "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
{ "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
{ "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
{ "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
{ "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
{ "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
{ "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
{ "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
{ "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
{ "", 0, 0, 0, 0 },
};
#define PM_DBG_MAX_REG_SETS 4
static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
static int pm_dbg_get_regset_size(void)
{
static int regset_size;
if (regset_size == 0) {
int i = 0;
while (pm_dbg_reg_modules[i].name[0] != 0) {
regset_size += pm_dbg_reg_modules[i].high +
4 - pm_dbg_reg_modules[i].low;
i++;
}
}
return regset_size;
}
static int pm_dbg_show_regs(struct seq_file *s, void *unused)
{
int i, j;
unsigned long val;
int reg_set = (int)s->private;
u32 *ptr;
void *store = NULL;
int regs;
int linefeed;
if (reg_set == 0) {
store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
ptr = store;
pm_dbg_regset_store(ptr);
} else {
ptr = pm_dbg_reg_set[reg_set - 1];
}
i = 0;
while (pm_dbg_reg_modules[i].name[0] != 0) {
regs = 0;
linefeed = 0;
if (pm_dbg_reg_modules[i].type == MOD_CM)
seq_printf(s, "MOD: CM_%s (%08x)\n",
pm_dbg_reg_modules[i].name,
(u32)(OMAP3430_CM_BASE +
pm_dbg_reg_modules[i].offset));
else
seq_printf(s, "MOD: PRM_%s (%08x)\n",
pm_dbg_reg_modules[i].name,
(u32)(OMAP3430_PRM_BASE +
pm_dbg_reg_modules[i].offset));
for (j = pm_dbg_reg_modules[i].low;
j <= pm_dbg_reg_modules[i].high; j += 4) {
val = *(ptr++);
if (val != 0) {
regs++;
if (linefeed) {
seq_printf(s, "\n");
linefeed = 0;
}
seq_printf(s, " %02x => %08lx", j, val);
if (regs % 4 == 0)
linefeed = 1;
}
}
seq_printf(s, "\n");
i++;
}
if (store != NULL)
kfree(store);
return 0;
}
static void pm_dbg_regset_store(u32 *ptr)
{
int i, j;
u32 val;
i = 0;
while (pm_dbg_reg_modules[i].name[0] != 0) {
for (j = pm_dbg_reg_modules[i].low;
j <= pm_dbg_reg_modules[i].high; j += 4) {
if (pm_dbg_reg_modules[i].type == MOD_CM)
val = cm_read_mod_reg(
pm_dbg_reg_modules[i].offset, j);
else
val = prm_read_mod_reg(
pm_dbg_reg_modules[i].offset, j);
*(ptr++) = val;
}
i++;
}
}
int pm_dbg_regset_save(int reg_set)
{
if (pm_dbg_reg_set[reg_set-1] == NULL)
return -EINVAL;
pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
return 0;
}
static const char pwrdm_state_names[][4] = {
"OFF",
"RET",
"INA",
"ON"
};
void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
{
s64 t;
if (!pm_dbg_init_done)
return ;
/* Update timer for previous state */
t = sched_clock();
pwrdm->state_timer[prev] += t - pwrdm->timer;
pwrdm->timer = t;
}
static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
{
struct seq_file *s = (struct seq_file *)user;
if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
strcmp(clkdm->name, "wkup_clkdm") == 0 ||
strncmp(clkdm->name, "dpll", 4) == 0)
return 0;
seq_printf(s, "%s->%s (%d)", clkdm->name,
clkdm->pwrdm.ptr->name,
atomic_read(&clkdm->usecount));
seq_printf(s, "\n");
return 0;
}
static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
{
struct seq_file *s = (struct seq_file *)user;
int i;
if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
strncmp(pwrdm->name, "dpll", 4) == 0)
return 0;
if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
seq_printf(s, "%s (%s)", pwrdm->name,
pwrdm_state_names[pwrdm->state]);
for (i = 0; i < 4; i++)
seq_printf(s, ",%s:%d", pwrdm_state_names[i],
pwrdm->state_counter[i]);
seq_printf(s, "\n");
return 0;
}
static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
{
struct seq_file *s = (struct seq_file *)user;
int i;
if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
strncmp(pwrdm->name, "dpll", 4) == 0)
return 0;
pwrdm_state_switch(pwrdm);
seq_printf(s, "%s (%s)", pwrdm->name,
pwrdm_state_names[pwrdm->state]);
for (i = 0; i < 4; i++)
seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
pwrdm->state_timer[i]);
seq_printf(s, "\n");
return 0;
}
static int pm_dbg_show_counters(struct seq_file *s, void *unused)
{
pwrdm_for_each(pwrdm_dbg_show_counter, s);
clkdm_for_each(clkdm_dbg_show_counter, s);
return 0;
}
static int pm_dbg_show_timers(struct seq_file *s, void *unused)
{
pwrdm_for_each(pwrdm_dbg_show_timer, s);
return 0;
}
static int pm_dbg_open(struct inode *inode, struct file *file)
{
switch ((int)inode->i_private) {
case DEBUG_FILE_COUNTERS:
return single_open(file, pm_dbg_show_counters,
&inode->i_private);
case DEBUG_FILE_TIMERS:
default:
return single_open(file, pm_dbg_show_timers,
&inode->i_private);
};
}
static int pm_dbg_reg_open(struct inode *inode, struct file *file)
{
return single_open(file, pm_dbg_show_regs, inode->i_private);
}
static const struct file_operations debug_fops = {
.open = pm_dbg_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static const struct file_operations debug_reg_fops = {
.open = pm_dbg_reg_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
int pm_dbg_regset_init(int reg_set)
{
char name[2];
if (!pm_dbg_init_done)
pm_dbg_init();
if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
pm_dbg_reg_set[reg_set-1] != NULL)
return -EINVAL;
pm_dbg_reg_set[reg_set-1] =
kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
if (pm_dbg_reg_set[reg_set-1] == NULL)
return -ENOMEM;
if (pm_dbg_dir != NULL) {
sprintf(name, "%d", reg_set);
(void) debugfs_create_file(name, S_IRUGO,
pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
}
return 0;
}
static int pwrdm_suspend_get(void *data, u64 *val)
{
*val = omap3_pm_get_suspend_state((struct powerdomain *)data);
if (*val >= 0)
return 0;
return *val;
}
static int pwrdm_suspend_set(void *data, u64 val)
{
return omap3_pm_set_suspend_state((struct powerdomain *)data, (int)val);
}
DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
pwrdm_suspend_set, "%llu\n");
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
{
int i;
s64 t;
struct dentry *d;
t = sched_clock();
for (i = 0; i < 4; i++)
pwrdm->state_timer[i] = 0;
pwrdm->timer = t;
if (strncmp(pwrdm->name, "dpll", 4) == 0)
return 0;
d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
(void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
(void *)pwrdm, &pwrdm_suspend_fops);
return 0;
}
static int __init pm_dbg_init(void)
{
int i;
struct dentry *d;
char name[2];
if (pm_dbg_init_done)
return 0;
if (cpu_is_omap34xx())
pm_dbg_reg_modules = omap3_pm_reg_modules;
else {
printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
return -ENODEV;
}
d = debugfs_create_dir("pm_debug", NULL);
if (IS_ERR(d))
return PTR_ERR(d);
(void) debugfs_create_file("count", S_IRUGO,
d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
(void) debugfs_create_file("time", S_IRUGO,
d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
pwrdm_for_each(pwrdms_setup, (void *)d);
pm_dbg_dir = debugfs_create_dir("registers", d);
if (IS_ERR(pm_dbg_dir))
return PTR_ERR(pm_dbg_dir);
(void) debugfs_create_file("current", S_IRUGO,
pm_dbg_dir, (void *)0, &debug_reg_fops);
for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
if (pm_dbg_reg_set[i] != NULL) {
sprintf(name, "%d", i+1);
(void) debugfs_create_file(name, S_IRUGO,
pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
}
pm_dbg_init_done = 1;
return 0;
}
arch_initcall(pm_dbg_init);
#else
void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) {}
#endif

11
arch/arm/mach-omap2/pm.h
Visa fil

@@ -11,12 +11,23 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PM_H
#define __ARCH_ARM_MACH_OMAP2_PM_H
#include <mach/powerdomain.h>
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
#ifdef CONFIG_PM_DEBUG
extern void omap2_pm_dump(int mode, int resume, unsigned int us);
extern int omap2_pm_debug;
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
extern int pm_dbg_regset_save(int reg_set);
extern int pm_dbg_regset_init(int reg_set);
#else
#define omap2_pm_dump(mode, resume, us) do {} while (0);
#define omap2_pm_debug 0
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
#define pm_dbg_regset_save(reg_set) do {} while (0);
#define pm_dbg_regset_init(reg_set) do {} while (0);
#endif /* CONFIG_PM_DEBUG */
extern void omap24xx_idle_loop_suspend(void);

4
arch/arm/mach-omap2/pm24xx.c
Visa fil

@@ -333,7 +333,7 @@ static struct platform_suspend_ops omap_pm_ops = {
.valid = suspend_valid_only_mem,
};
static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused)
{
omap2_clkdm_allow_idle(clkdm);
return 0;
@@ -385,7 +385,7 @@ static void __init prcm_setup_regs(void)
omap2_clkdm_sleep(gfx_clkdm);
/* Enable clockdomain hardware-supervised control for all clkdms */
clkdm_for_each(_pm_clkdm_enable_hwsup);
clkdm_for_each(_pm_clkdm_enable_hwsup, NULL);
/* Enable clock autoidle for all domains */
cm_write_mod_reg(OMAP24XX_AUTO_CAM |

40
arch/arm/mach-omap2/pm34xx.c
Visa fil

@@ -170,6 +170,8 @@ static void omap_sram_idle(void)
printk(KERN_ERR "Invalid mpu state in sram_idle\n");
return;
}
pwrdm_pre_transition();
omap2_gpio_prepare_for_retention();
omap_uart_prepare_idle(0);
omap_uart_prepare_idle(1);
@@ -182,6 +184,9 @@ static void omap_sram_idle(void)
omap_uart_resume_idle(1);
omap_uart_resume_idle(0);
omap2_gpio_resume_after_retention();
pwrdm_post_transition();
}
/*
@@ -271,6 +276,7 @@ static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
if (sleep_switch) {
omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
pwrdm_wait_transition(pwrdm);
pwrdm_state_switch(pwrdm);
}
err:
@@ -658,14 +664,38 @@ static void __init prcm_setup_regs(void)
omap3_d2d_idle();
}
static int __init pwrdms_setup(struct powerdomain *pwrdm)
int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
{
struct power_state *pwrst;
list_for_each_entry(pwrst, &pwrst_list, node) {
if (pwrst->pwrdm == pwrdm)
return pwrst->next_state;
}
return -EINVAL;
}
int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
{
struct power_state *pwrst;
list_for_each_entry(pwrst, &pwrst_list, node) {
if (pwrst->pwrdm == pwrdm) {
pwrst->next_state = state;
return 0;
}
}
return -EINVAL;
}
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
struct power_state *pwrst;
if (!pwrdm->pwrsts)
return 0;
pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
if (!pwrst)
return -ENOMEM;
pwrst->pwrdm = pwrdm;
@@ -683,7 +713,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
* supported. Initiate sleep transition for other clockdomains, if
* they are not used
*/
static int __init clkdms_setup(struct clockdomain *clkdm)
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
{
if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
omap2_clkdm_allow_idle(clkdm);
@@ -716,13 +746,13 @@ static int __init omap3_pm_init(void)
goto err1;
}
ret = pwrdm_for_each(pwrdms_setup);
ret = pwrdm_for_each(pwrdms_setup, NULL);
if (ret) {
printk(KERN_ERR "Failed to setup powerdomains\n");
goto err2;
}
(void) clkdm_for_each(clkdms_setup);
(void) clkdm_for_each(clkdms_setup, NULL);
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
if (mpu_pwrdm == NULL) {

114
arch/arm/mach-omap2/powerdomain.c
Visa fil

@@ -35,6 +35,13 @@
#include <mach/powerdomain.h>
#include <mach/clockdomain.h>
#include "pm.h"
enum {
PWRDM_STATE_NOW = 0,
PWRDM_STATE_PREV,
};
/* pwrdm_list contains all registered struct powerdomains */
static LIST_HEAD(pwrdm_list);
@@ -83,7 +90,7 @@ static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
if (!pwrdm || !deps || !omap_chip_is(pwrdm->omap_chip))
return ERR_PTR(-EINVAL);
for (pd = deps; pd; pd++) {
for (pd = deps; pd->pwrdm_name; pd++) {
if (!omap_chip_is(pd->omap_chip))
continue;
@@ -96,12 +103,71 @@ static struct powerdomain *_pwrdm_deps_lookup(struct powerdomain *pwrdm,
}
if (!pd)
if (!pd->pwrdm_name)
return ERR_PTR(-ENOENT);
return pd->pwrdm;
}
static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
{
int prev;
int state;
if (pwrdm == NULL)
return -EINVAL;
state = pwrdm_read_pwrst(pwrdm);
switch (flag) {
case PWRDM_STATE_NOW:
prev = pwrdm->state;
break;
case PWRDM_STATE_PREV:
prev = pwrdm_read_prev_pwrst(pwrdm);
if (pwrdm->state != prev)
pwrdm->state_counter[prev]++;
break;
default:
return -EINVAL;
}
if (state != prev)
pwrdm->state_counter[state]++;
pm_dbg_update_time(pwrdm, prev);
pwrdm->state = state;
return 0;
}
static int _pwrdm_pre_transition_cb(struct powerdomain *pwrdm, void *unused)
{
pwrdm_clear_all_prev_pwrst(pwrdm);
_pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
return 0;
}
static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
{
_pwrdm_state_switch(pwrdm, PWRDM_STATE_PREV);
return 0;
}
static __init void _pwrdm_setup(struct powerdomain *pwrdm)
{
int i;
for (i = 0; i < 4; i++)
pwrdm->state_counter[i] = 0;
pwrdm_wait_transition(pwrdm);
pwrdm->state = pwrdm_read_pwrst(pwrdm);
pwrdm->state_counter[pwrdm->state] = 1;
}
/* Public functions */
@@ -117,9 +183,12 @@ void pwrdm_init(struct powerdomain **pwrdm_list)
{
struct powerdomain **p = NULL;
if (pwrdm_list)
for (p = pwrdm_list; *p; p++)
if (pwrdm_list) {
for (p = pwrdm_list; *p; p++) {
pwrdm_register(*p);
_pwrdm_setup(*p);
}
}
}
/**
@@ -217,7 +286,8 @@ struct powerdomain *pwrdm_lookup(const char *name)
* anything else to indicate failure; or -EINVAL if the function
* pointer is null.
*/
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
void *user)
{
struct powerdomain *temp_pwrdm;
unsigned long flags;
@@ -228,7 +298,7 @@ int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm))
read_lock_irqsave(&pwrdm_rwlock, flags);
list_for_each_entry(temp_pwrdm, &pwrdm_list, node) {
ret = (*fn)(temp_pwrdm);
ret = (*fn)(temp_pwrdm, user);
if (ret)
break;
}
@@ -1110,4 +1180,36 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
return 0;
}
int pwrdm_state_switch(struct powerdomain *pwrdm)
{
return _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
}
int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
{
if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
pwrdm_wait_transition(clkdm->pwrdm.ptr);
return pwrdm_state_switch(clkdm->pwrdm.ptr);
}
return -EINVAL;
}
int pwrdm_clk_state_switch(struct clk *clk)
{
if (clk != NULL && clk->clkdm != NULL)
return pwrdm_clkdm_state_switch(clk->clkdm);
return -EINVAL;
}
int pwrdm_pre_transition(void)
{
pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
return 0;
}
int pwrdm_post_transition(void)
{
pwrdm_for_each(_pwrdm_post_transition_cb, NULL);
return 0;
}

6
arch/arm/mach-omap2/prm.h
Visa fil

@@ -17,11 +17,11 @@
#include "prcm-common.h"
#define OMAP2420_PRM_REGADDR(module, reg) \
IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
#define OMAP2430_PRM_REGADDR(module, reg) \
IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
#define OMAP34XX_PRM_REGADDR(module, reg) \
IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
/*
* Architecture-specific global PRM registers

6
arch/arm/mach-omap2/sdrc.h
Visa fil

@@ -48,9 +48,9 @@ static inline u32 sms_read_reg(u16 reg)
return __raw_readl(OMAP_SMS_REGADDR(reg));
}
#else
#define OMAP242X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
#define OMAP243X_SDRC_REGADDR(reg) IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
#define OMAP34XX_SDRC_REGADDR(reg) IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
#define OMAP242X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
#define OMAP243X_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
#define OMAP34XX_SDRC_REGADDR(reg) OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
#endif /* __ASSEMBLER__ */
#endif

79
arch/arm/mach-omap2/serial.c
Visa fil

@@ -73,7 +73,7 @@ static LIST_HEAD(uart_list);
static struct plat_serial8250_port serial_platform_data0[] = {
{
.membase = IO_ADDRESS(OMAP_UART1_BASE),
.membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
.mapbase = OMAP_UART1_BASE,
.irq = 72,
.flags = UPF_BOOT_AUTOCONF,
@@ -87,7 +87,7 @@ static struct plat_serial8250_port serial_platform_data0[] = {
static struct plat_serial8250_port serial_platform_data1[] = {
{
.membase = IO_ADDRESS(OMAP_UART2_BASE),
.membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
.mapbase = OMAP_UART2_BASE,
.irq = 73,
.flags = UPF_BOOT_AUTOCONF,
@@ -101,7 +101,7 @@ static struct plat_serial8250_port serial_platform_data1[] = {
static struct plat_serial8250_port serial_platform_data2[] = {
{
.membase = IO_ADDRESS(OMAP_UART3_BASE),
.membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
.mapbase = OMAP_UART3_BASE,
.irq = 74,
.flags = UPF_BOOT_AUTOCONF,
@@ -109,10 +109,35 @@ static struct plat_serial8250_port serial_platform_data2[] = {
.regshift = 2,
.uartclk = OMAP24XX_BASE_BAUD * 16,
}, {
#ifdef CONFIG_ARCH_OMAP4
.membase = IO_ADDRESS(OMAP_UART4_BASE),
.mapbase = OMAP_UART4_BASE,
.irq = 70,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = OMAP24XX_BASE_BAUD * 16,
}, {
#endif
.flags = 0
}
};
#ifdef CONFIG_ARCH_OMAP4
static struct plat_serial8250_port serial_platform_data3[] = {
{
.membase = IO_ADDRESS(OMAP_UART4_BASE),
.mapbase = OMAP_UART4_BASE,
.irq = 70,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = OMAP24XX_BASE_BAUD * 16,
}, {
.flags = 0
}
};
#endif
static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
int offset)
{
@@ -460,7 +485,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
uart->padconf = 0;
}
p->flags |= UPF_SHARE_IRQ;
p->irqflags |= IRQF_SHARED;
ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
"serial idle", (void *)uart);
WARN_ON(ret);
@@ -550,12 +575,22 @@ static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
},
},
},
#ifdef CONFIG_ARCH_OMAP4
{
.pdev = {
.name = "serial8250",
.id = 3
.dev = {
.platform_data = serial_platform_data3,
},
},
},
#endif
};
void __init omap_serial_init(void)
void __init omap_serial_early_init(void)
{
int i;
const struct omap_uart_config *info;
char name[16];
/*
@@ -564,23 +599,12 @@ void __init omap_serial_init(void)
* if not needed.
*/
info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
if (info == NULL)
return;
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
struct omap_uart_state *uart = &omap_uart[i];
struct platform_device *pdev = &uart->pdev;
struct device *dev = &pdev->dev;
struct plat_serial8250_port *p = dev->platform_data;
if (!(info->enabled_uarts & (1 << i))) {
p->membase = NULL;
p->mapbase = 0;
continue;
}
sprintf(name, "uart%d_ick", i+1);
uart->ick = clk_get(NULL, name);
if (IS_ERR(uart->ick)) {
@@ -595,8 +619,11 @@ void __init omap_serial_init(void)
uart->fck = NULL;
}
if (!uart->ick || !uart->fck)
continue;
/* FIXME: Remove this once the clkdev is ready */
if (!cpu_is_omap44xx()) {
if (!uart->ick || !uart->fck)
continue;
}
uart->num = i;
p->private_data = uart;
@@ -607,6 +634,18 @@ void __init omap_serial_init(void)
p->irq += 32;
omap_uart_enable_clocks(uart);
}
}
void __init omap_serial_init(void)
{
int i;
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
struct omap_uart_state *uart = &omap_uart[i];
struct platform_device *pdev = &uart->pdev;
struct device *dev = &pdev->dev;
omap_uart_reset(uart);
omap_uart_idle_init(uart);

4
arch/arm/mach-omap2/sram242x.S
Visa fil

@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl:
prcm_mask_val:
.word 0xFFFF3FFC
omap242x_sdi_timer_32ksynct_cr:
.word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
.word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
ENTRY(omap242x_sram_ddr_init_sz)
.word . - omap242x_sram_ddr_init
@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl:
ddr_prcm_mask_val:
.word 0xFFFF3FFC
omap242x_srs_timer_32ksynct:
.word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
.word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
ENTRY(omap242x_sram_reprogram_sdrc_sz)
.word . - omap242x_sram_reprogram_sdrc

4
arch/arm/mach-omap2/sram243x.S
Visa fil

@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl:
prcm_mask_val:
.word 0xFFFF3FFC
omap243x_sdi_timer_32ksynct_cr:
.word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
.word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
ENTRY(omap243x_sram_ddr_init_sz)
.word . - omap243x_sram_ddr_init
@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl:
ddr_prcm_mask_val:
.word 0xFFFF3FFC
omap243x_srs_timer_32ksynct:
.word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
.word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
ENTRY(omap243x_sram_reprogram_sdrc_sz)
.word . - omap243x_sram_reprogram_sdrc

2
arch/arm/mach-omap2/timer-gp.c
Visa fil

@@ -231,7 +231,7 @@ static void __init omap2_gp_clocksource_init(void)
static void __init omap2_gp_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
twd_base = IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
#endif
omap_dm_timer_init();

12
arch/arm/mach-omap2/usb-musb.c
Visa fil

@@ -31,15 +31,6 @@
#include <mach/mux.h>
#include <mach/usb.h>
#define OTG_SYSCONFIG (OMAP34XX_HSUSB_OTG_BASE + 0x404)
static void __init usb_musb_pm_init(void)
{
/* Ensure force-idle mode for OTG controller */
if (cpu_is_omap34xx())
omap_writel(0, OTG_SYSCONFIG);
}
#ifdef CONFIG_USB_MUSB_SOC
static struct resource musb_resources[] = {
@@ -173,13 +164,10 @@ void __init usb_musb_init(void)
printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n");
return;
}
usb_musb_pm_init();
}
#else
void __init usb_musb_init(void)
{
usb_musb_pm_init();
}
#endif /* CONFIG_USB_MUSB_SOC */