arm64: Fix single stepping in kernel traps
Software Step exception is missing after stepping a trapped instruction. Ensure SPSR.SS gets set to 0 after emulating/skipping a trapped instruction before doing ERET. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Julien Thierry <julien.thierry@arm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [will: replaced AARCH32_INSN_SIZE with 4] Signed-off-by: Will Deacon <will.deacon@arm.com>
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@@ -431,7 +431,7 @@ ret:
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pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
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current->comm, (unsigned long)current->pid, regs->pc);
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regs->pc += 4;
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arm64_skip_faulting_instruction(regs, 4);
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return 0;
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fault:
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@@ -512,7 +512,7 @@ ret:
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pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
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current->comm, (unsigned long)current->pid, regs->pc);
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regs->pc += 4;
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arm64_skip_faulting_instruction(regs, 4);
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return 0;
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}
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@@ -586,14 +586,14 @@ static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
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static int a32_setend_handler(struct pt_regs *regs, u32 instr)
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{
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int rc = compat_setend_handler(regs, (instr >> 9) & 1);
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regs->pc += 4;
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arm64_skip_faulting_instruction(regs, 4);
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return rc;
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}
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static int t16_setend_handler(struct pt_regs *regs, u32 instr)
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{
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int rc = compat_setend_handler(regs, (instr >> 3) & 1);
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regs->pc += 2;
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arm64_skip_faulting_instruction(regs, 2);
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return rc;
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}
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