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ASoC: da7219: Update PLL ranges and dividers to improve locking

Telusuri Sumber 
The expected MCLK frequency ranges and the associated dividers
are updated to improve PLL locking in a corner scenario, with low
MCLK frequency near an input divider change boundary.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Adam Thomson
2016-04-19 15:19:02 +01:00
committed by Mark Brown
orang tua f55532a0c0
melakukan 63a450aa4d
2 mengubah file dengan 24 tambahan dan 24 penghapusan
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20
sound/soc/codecs/da7219.h
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@@ -194,11 +194,11 @@
/* DA7219_PLL_CTRL = 0x20 */
#define DA7219_PLL_INDIV_SHIFT 2
#define DA7219_PLL_INDIV_MASK (0x7 << 2)
#define DA7219_PLL_INDIV_2_5_MHZ (0x0 << 2)
#define DA7219_PLL_INDIV_5_10_MHZ (0x1 << 2)
#define DA7219_PLL_INDIV_10_20_MHZ (0x2 << 2)
#define DA7219_PLL_INDIV_20_40_MHZ (0x3 << 2)
#define DA7219_PLL_INDIV_40_54_MHZ (0x4 << 2)
#define DA7219_PLL_INDIV_2_TO_4_5_MHZ (0x0 << 2)
#define DA7219_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 2)
#define DA7219_PLL_INDIV_9_TO_18_MHZ (0x2 << 2)
#define DA7219_PLL_INDIV_18_TO_36_MHZ (0x3 << 2)
#define DA7219_PLL_INDIV_36_TO_54_MHZ (0x4 << 2)
#define DA7219_PLL_MCLK_SQR_EN_SHIFT 5
#define DA7219_PLL_MCLK_SQR_EN_MASK (0x1 << 5)
#define DA7219_PLL_MODE_SHIFT 6
@@ -761,11 +761,11 @@
#define DA7219_PLL_FREQ_OUT_98304 98304000
/* PLL Frequency Dividers */
#define DA7219_PLL_INDIV_2_5_MHZ_VAL 1
#define DA7219_PLL_INDIV_5_10_MHZ_VAL 2
#define DA7219_PLL_INDIV_10_20_MHZ_VAL 4
#define DA7219_PLL_INDIV_20_40_MHZ_VAL 8
#define DA7219_PLL_INDIV_40_54_MHZ_VAL 16
#define DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL 1
#define DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL 2
#define DA7219_PLL_INDIV_9_TO_18_MHZ_VAL 4
#define DA7219_PLL_INDIV_18_TO_36_MHZ_VAL 8
#define DA7219_PLL_INDIV_36_TO_54_MHZ_VAL 16
/* SRM */
#define DA7219_SRM_CHECK_RETRIES 8