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ASoC: da7219: Update PLL ranges and dividers to improve locking

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The expected MCLK frequency ranges and the associated dividers
are updated to improve PLL locking in a corner scenario, with low
MCLK frequency near an input divider change boundary.

Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
此提交包含在：
Adam Thomson
2016-04-19 15:19:02 +01:00
提交者 Mark Brown
父節點 f55532a0c0
當前提交 63a450aa4d
共有 2 個檔案被更改，包括 24 行新增 和 24 行删除
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28
sound/soc/codecs/da7219.c
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@@ -1079,21 +1079,21 @@ static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
dev_err(codec->dev, "PLL input clock %d below valid range\n",
da7219->mclk_rate);
return -EINVAL;
} else if (da7219->mclk_rate <= 5000000) {
indiv_bits = DA7219_PLL_INDIV_2_5_MHZ;
indiv = DA7219_PLL_INDIV_2_5_MHZ_VAL;
} else if (da7219->mclk_rate <= 10000000) {
indiv_bits = DA7219_PLL_INDIV_5_10_MHZ;
indiv = DA7219_PLL_INDIV_5_10_MHZ_VAL;
} else if (da7219->mclk_rate <= 20000000) {
indiv_bits = DA7219_PLL_INDIV_10_20_MHZ;
indiv = DA7219_PLL_INDIV_10_20_MHZ_VAL;
} else if (da7219->mclk_rate <= 40000000) {
indiv_bits = DA7219_PLL_INDIV_20_40_MHZ;
indiv = DA7219_PLL_INDIV_20_40_MHZ_VAL;
} else if (da7219->mclk_rate <= 4500000) {
indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ;
indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL;
} else if (da7219->mclk_rate <= 9000000) {
indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ;
indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL;
} else if (da7219->mclk_rate <= 18000000) {
indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ;
indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL;
} else if (da7219->mclk_rate <= 36000000) {
indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ;
indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL;
} else if (da7219->mclk_rate <= 54000000) {
indiv_bits = DA7219_PLL_INDIV_40_54_MHZ;
indiv = DA7219_PLL_INDIV_40_54_MHZ_VAL;
indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ;
indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL;
} else {
dev_err(codec->dev, "PLL input clock %d above valid range\n",
da7219->mclk_rate);