i40e: fix reading LLDP configuration
Previous method for reading LLDP config was based on hard-coded offsets. It happened to work, because of structured architecture of the NVM memory. In the new approach, known as FLAT, we need to calculate the absolute address, instead of using relative values. Needed defines for memory location were added. Signed-off-by: Mariusz Stachura <mariusz.stachura@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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committed by
Jeff Kirsher

parent
f5254429e1
commit
6334f2432f
@@ -1233,7 +1233,8 @@ struct i40e_hw_port_stats {
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/* Checksum and Shadow RAM pointers */
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#define I40E_SR_NVM_CONTROL_WORD 0x00
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#define I40E_SR_EMP_MODULE_PTR 0x0F
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#define I40E_EMP_MODULE_PTR 0x0F
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#define I40E_SR_EMP_MODULE_PTR 0x48
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#define I40E_NVM_OEM_VER_OFF 0x83
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#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
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#define I40E_SR_NVM_WAKE_ON_LAN 0x19
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@@ -1249,6 +1250,9 @@ struct i40e_hw_port_stats {
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#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
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#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
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#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
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#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
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#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
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#define I40E_PTR_TYPE BIT(15)
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/* Shadow RAM related */
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#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
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@@ -1362,6 +1366,10 @@ enum i40e_reset_type {
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I40E_RESET_EMPR = 3,
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};
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/* IEEE 802.1AB LLDP Agent Variables from NVM */
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#define I40E_NVM_LLDP_CFG_PTR 0x06
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#define I40E_SR_LLDP_CFG_PTR 0x31
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/* RSS Hash Table Size */
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#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
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