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ARM: sirf: enable sparse IRQ

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Now that both irqchips for sirf are converted to not rely on
legacy domains, let's move all of the platform over to sparse
IRQ.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2013-03-19 12:19:01 +01:00
parent 60dbd7680f
commit 630be7ea2f
3 changed files with 3 additions and 17 deletions
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1
arch/arm/Kconfig
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@@ -427,6 +427,7 @@ config ARCH_SIRF
select PINCTRL select PINCTRL
select PINCTRL_SIRF select PINCTRL_SIRF
select USE_OF select USE_OF
select SPARSE_IRQ
help help
Support for CSR SiRFprimaII/Marco/Polo platforms Support for CSR SiRFprimaII/Marco/Polo platforms

2
arch/arm/mach-prima2/common.c
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@@ -45,6 +45,7 @@ static const char *atlas6_dt_match[] __initdata = {
DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */ /* Maintainer: Barry Song <baohua.song@csr.com> */
.nr_irqs = 128,
.map_io = sirfsoc_map_io, .map_io = sirfsoc_map_io,
.init_irq = irqchip_init, .init_irq = irqchip_init,
.init_time = sirfsoc_prima2_timer_init, .init_time = sirfsoc_prima2_timer_init,
@@ -63,6 +64,7 @@ static const char *prima2_dt_match[] __initdata = {
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */ /* Maintainer: Barry Song <baohua.song@csr.com> */
.nr_irqs = 128,
.map_io = sirfsoc_map_io, .map_io = sirfsoc_map_io,
.init_irq = irqchip_init, .init_irq = irqchip_init,
.init_time = sirfsoc_prima2_timer_init, .init_time = sirfsoc_prima2_timer_init,

17
arch/arm/mach-prima2/include/mach/irqs.h
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@@ -1,17 +0,0 @@
/*
* arch/arm/mach-prima2/include/mach/irqs.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#define SIRFSOC_INTENAL_IRQ_START 0
#define SIRFSOC_INTENAL_IRQ_END 127
#define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1)
#define NR_IRQS 288
#endif