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drm/i915/uc: Move uC WOPCM setup in uc_init_hw

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The register we write are not WOPCM regs but uC ones related to how
GuC and HuC are going to use the WOPCM, so it makes logical sense
for them to be programmed as part of uc_init_hw. The WOPCM map on the
other side is not uC-specific (although that is our main use-case), so
keep that separate.

v2: move write_and_verify to uncore, fix log, re-use err_out tag,
    add intel_wopcm_guc_base, fix log

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730230743.19542-2-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio
2019-07-30 16:07:40 -07:00
committed by Chris Wilson
parent 602776f96b
commit 63064d822c
6 changed files with 76 additions and 80 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
drivers/gpu/drm/i915/intel_wopcm.c
View File

@@ -224,71 +224,3 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
return 0;
}
static int
write_and_verify(struct intel_gt *gt,
i915_reg_t reg, u32 val, u32 mask, u32 locked_bit)
{
struct intel_uncore *uncore = gt->uncore;
u32 reg_val;
GEM_BUG_ON(val & ~mask);
intel_uncore_write(uncore, reg, val);
reg_val = intel_uncore_read(uncore, reg);
return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
}
/**
* intel_wopcm_init_hw() - Setup GuC WOPCM registers.
* @wopcm: pointer to intel_wopcm.
* @gt: pointer to the containing GT
*
* Setup the GuC WOPCM size and offset registers with the calculated values. It
* will verify the register values to make sure the registers are locked with
* correct values.
*
* Return: 0 on success. -EIO if registers were locked with incorrect values.
*/
int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt)
{
struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
struct intel_uncore *uncore = gt->uncore;
u32 huc_agent;
u32 mask;
int err;
if (!USES_GUC(i915))
return 0;
GEM_BUG_ON(!HAS_GT_UC(i915));
GEM_BUG_ON(!wopcm->guc.size);
GEM_BUG_ON(!wopcm->guc.base);
err = write_and_verify(gt, GUC_WOPCM_SIZE, wopcm->guc.size,
GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
GUC_WOPCM_SIZE_LOCKED);
if (err)
goto err_out;
huc_agent = USES_HUC(i915) ? HUC_LOADING_AGENT_GUC : 0;
mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
err = write_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
wopcm->guc.base | huc_agent, mask,
GUC_WOPCM_OFFSET_VALID);
if (err)
goto err_out;
return 0;
err_out:
DRM_ERROR("Failed to init WOPCM registers:\n");
DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
DRM_ERROR("GUC_WOPCM_SIZE=%#x\n",
intel_uncore_read(uncore, GUC_WOPCM_SIZE));
return err;
}