Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "API: - Remove VLA usage - Add cryptostat user-space interface - Add notifier for new crypto algorithms Algorithms: - Add OFB mode - Remove speck Drivers: - Remove x86/sha*-mb as they are buggy - Remove pcbc(aes) from x86/aesni - Improve performance of arm/ghash-ce by up to 85% - Implement CTS-CBC in arm64/aes-blk, faster by up to 50% - Remove PMULL based arm64/crc32 driver - Use PMULL in arm64/crct10dif - Add aes-ctr support in s5p-sss - Add caam/qi2 driver Others: - Pick better transform if one becomes available in crc-t10dif" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (124 commits) crypto: chelsio - Update ntx queue received from cxgb4 crypto: ccree - avoid implicit enum conversion crypto: caam - add SPDX license identifier to all files crypto: caam/qi - simplify CGR allocation, freeing crypto: mxs-dcp - make symbols 'sha1_null_hash' and 'sha256_null_hash' static crypto: arm64/aes-blk - ensure XTS mask is always loaded crypto: testmgr - fix sizeof() on COMP_BUF_SIZE crypto: chtls - remove set but not used variable 'csk' crypto: axis - fix platform_no_drv_owner.cocci warnings crypto: x86/aes-ni - fix build error following fpu template removal crypto: arm64/aes - fix handling sub-block CTS-CBC inputs crypto: caam/qi2 - avoid double export crypto: mxs-dcp - Fix AES issues crypto: mxs-dcp - Fix SHA null hashes and output length crypto: mxs-dcp - Implement sha import/export crypto: aegis/generic - fix for big endian systems crypto: morus/generic - fix for big endian systems crypto: lrw - fix rebase error after out of bounds fix crypto: cavium/nitrox - use pci_alloc_irq_vectors() while enabling MSI-X. crypto: cavium/nitrox - NITROX command queue changes. ...
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@@ -520,10 +520,20 @@ setup_sge_txq_uld(struct adapter *adap, unsigned int uld_type,
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txq_info = kzalloc(sizeof(*txq_info), GFP_KERNEL);
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if (!txq_info)
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return -ENOMEM;
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if (uld_type == CXGB4_ULD_CRYPTO) {
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i = min_t(int, adap->vres.ncrypto_fc,
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num_online_cpus());
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txq_info->ntxq = rounddown(i, adap->params.nports);
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if (txq_info->ntxq <= 0) {
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dev_warn(adap->pdev_dev, "Crypto Tx Queues can't be zero\n");
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kfree(txq_info);
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return -EINVAL;
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}
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i = min_t(int, uld_info->ntxq, num_online_cpus());
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txq_info->ntxq = roundup(i, adap->params.nports);
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} else {
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i = min_t(int, uld_info->ntxq, num_online_cpus());
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txq_info->ntxq = roundup(i, adap->params.nports);
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}
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txq_info->uldtxq = kcalloc(txq_info->ntxq, sizeof(struct sge_uld_txq),
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GFP_KERNEL);
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if (!txq_info->uldtxq) {
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@@ -546,11 +556,14 @@ static void uld_queue_init(struct adapter *adap, unsigned int uld_type,
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struct cxgb4_lld_info *lli)
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{
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struct sge_uld_rxq_info *rxq_info = adap->sge.uld_rxq_info[uld_type];
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int tx_uld_type = TX_ULD(uld_type);
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struct sge_uld_txq_info *txq_info = adap->sge.uld_txq_info[tx_uld_type];
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lli->rxq_ids = rxq_info->rspq_id;
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lli->nrxq = rxq_info->nrxq;
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lli->ciq_ids = rxq_info->rspq_id + rxq_info->nrxq;
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lli->nciq = rxq_info->nciq;
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lli->ntxq = txq_info->ntxq;
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}
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int t4_uld_mem_alloc(struct adapter *adap)
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@@ -634,7 +647,6 @@ static void uld_init(struct adapter *adap, struct cxgb4_lld_info *lld)
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lld->ports = adap->port;
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lld->vr = &adap->vres;
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lld->mtus = adap->params.mtus;
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lld->ntxq = adap->sge.ofldqsets;
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lld->nchan = adap->params.nports;
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lld->nports = adap->params.nports;
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lld->wr_cred = adap->params.ofldq_wr_cred;
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