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sh: fix Transfer Size calculation in both DMA drivers

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Both the original arch/sh/drivers/dma/dma-sh.c and the new SH dmaengine drivers
do not take into account bits 3:2 of the Transfer Size field in the CHCR
register, besides, bit-field defines set bit 2, but the mask only passes bits
1:0 through. TS_16BLK and TS_32BLK macros are bogus too. This patch fixes all
these issues for sh7722 and sh7724, other CPUs stay unchanged and might need to
be fixed too.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Guennadi Liakhovetski
2010-02-03 14:44:12 +00:00
committed by Paul Mundt
parent fc4618575f
commit 623b4ac4bf
6 changed files with 114 additions and 51 deletions
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5
arch/sh/drivers/dma/dma-sh.c
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@@ -52,11 +52,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
*
* iterations to complete the transfer.
*/
static unsigned int ts_shift[] = TS_SHIFT;
static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
{
u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
return ts_shift[cnt];
}
/*