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Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-merge

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This commit is contained in:
Linus Torvalds
2006-01-09 10:03:44 -08:00
parent 44637a12f8 be42d5fa37
commit 6150c32589
287 changed files with 27070 additions and 5926 deletions
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2
include/asm-powerpc/abs_addr.h
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@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_ABS_ADDR_H
#define _ASM_POWERPC_ABS_ADDR_H
#ifdef __KERNEL__
#include <linux/config.h>
@@ -70,4 +71,5 @@ static inline unsigned long phys_to_abs(unsigned long pa)
#define iseries_hv_addr(virtaddr) \
(0x8000000000000000 | virt_to_abs(virtaddr))
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_ABS_ADDR_H */

2
include/asm-powerpc/agp.h
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@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_AGP_H
#define _ASM_POWERPC_AGP_H
#ifdef __KERNEL__
#include <asm/io.h>
@@ -18,4 +19,5 @@
#define free_gatt_pages(table, order) \
free_pages((unsigned long)(table), (order))
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_AGP_H */

3
include/asm-powerpc/asm-compat.h
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@@ -1,7 +1,6 @@
#ifndef _ASM_POWERPC_ASM_COMPAT_H
#define _ASM_POWERPC_ASM_COMPAT_H
#include <linux/config.h>
#include <asm/types.h>
#ifdef __ASSEMBLY__
@@ -41,6 +40,7 @@
#endif
#ifdef __KERNEL__
#ifdef CONFIG_IBM405_ERR77
/* Erratum #77 on the 405 means we need a sync or dcbt before every
* stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this.
@@ -51,5 +51,6 @@
#define PPC405_ERR77(ra,rb)
#define PPC405_ERR77_SYNC
#endif
#endif
#endif /* _ASM_POWERPC_ASM_COMPAT_H */

171
include/asm-powerpc/bootx.h Normal file
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@@ -0,0 +1,171 @@
/*
* This file describes the structure passed from the BootX application
* (for MacOS) when it is used to boot Linux.
*
* Written by Benjamin Herrenschmidt.
*/
#ifndef __ASM_BOOTX_H__
#define __ASM_BOOTX_H__
#include <asm/types.h>
#ifdef macintosh
#include <Types.h>
#include "linux_type_defs.h"
#endif
#ifdef macintosh
/* All this requires PowerPC alignment */
#pragma options align=power
#endif
/* On kernel entry:
*
* r3 = 0x426f6f58 ('BooX')
* r4 = pointer to boot_infos
* r5 = NULL
*
* Data and instruction translation disabled, interrupts
* disabled, kernel loaded at physical 0x00000000 on PCI
* machines (will be different on NuBus).
*/
#define BOOT_INFO_VERSION 5
#define BOOT_INFO_COMPATIBLE_VERSION 1
/* Bit in the architecture flag mask. More to be defined in
future versions. Note that either BOOT_ARCH_PCI or
BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
set additionally when BOOT_ARCH_NUBUS is set.
*/
#define BOOT_ARCH_PCI 0x00000001UL
#define BOOT_ARCH_NUBUS 0x00000002UL
#define BOOT_ARCH_NUBUS_PDM 0x00000010UL
#define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL
#define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL
/* Maximum number of ranges in phys memory map */
#define MAX_MEM_MAP_SIZE 26
/* This is the format of an element in the physical memory map. Note that
the map is optional and current BootX will only build it for pre-PCI
machines */
typedef struct boot_info_map_entry
{
__u32 physAddr; /* Physical starting address */
__u32 size; /* Size in bytes */
} boot_info_map_entry_t;
/* Here are the boot informations that are passed to the bootstrap
* Note that the kernel arguments and the device tree are appended
* at the end of this structure. */
typedef struct boot_infos
{
/* Version of this structure */
__u32 version;
/* backward compatible down to version: */
__u32 compatible_version;
/* NEW (vers. 2) this holds the current _logical_ base addr of
the frame buffer (for use by early boot message) */
__u8* logicalDisplayBase;
/* NEW (vers. 4) Apple's machine identification */
__u32 machineID;
/* NEW (vers. 4) Detected hw architecture */
__u32 architecture;
/* The device tree (internal addresses relative to the beginning of the tree,
* device tree offset relative to the beginning of this structure).
* On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
* field is 0.
*/
__u32 deviceTreeOffset; /* Device tree offset */
__u32 deviceTreeSize; /* Size of the device tree */
/* Some infos about the current MacOS display */
__u32 dispDeviceRect[4]; /* left,top,right,bottom */
__u32 dispDeviceDepth; /* (8, 16 or 32) */
__u8* dispDeviceBase; /* base address (physical) */
__u32 dispDeviceRowBytes; /* rowbytes (in bytes) */
__u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */
/* Optional offset in the registry to the current
* MacOS display. (Can be 0 when not detected) */
__u32 dispDeviceRegEntryOffset;
/* Optional pointer to boot ramdisk (offset from this structure) */
__u32 ramDisk;
__u32 ramDiskSize; /* size of ramdisk image */
/* Kernel command line arguments (offset from this structure) */
__u32 kernelParamsOffset;
/* ALL BELOW NEW (vers. 4) */
/* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
(non-PCI) only. On PCI, memory is contiguous and it's size is in the
device-tree. */
boot_info_map_entry_t
physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
__u32 physMemoryMapSize; /* How many entries in map */
/* The framebuffer size (optional, currently 0) */
__u32 frameBufferSize; /* Represents a max size, can be 0. */
/* NEW (vers. 5) */
/* Total params size (args + colormap + device tree + ramdisk) */
__u32 totalParamsSize;
} boot_infos_t;
#ifdef __KERNEL__
/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index
* is represented by 3 short words containing a 16 bits (unsigned) color
* component. Later versions may contain the gamma table for direct-color
* devices here.
*/
#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL)
/* BootX passes the device-tree using a format that comes from earlier
* ppc32 kernels. This used to match what is in prom.h, but not anymore
* so we now define it here
*/
struct bootx_dt_prop {
u32 name;
int length;
u32 value;
u32 next;
};
struct bootx_dt_node {
u32 unused0;
u32 unused1;
u32 phandle; /* not really available */
u32 unused2;
u32 unused3;
u32 unused4;
u32 unused5;
u32 full_name;
u32 properties;
u32 parent;
u32 child;
u32 sibling;
u32 next;
u32 allnext;
};
extern void bootx_init(unsigned long r4, unsigned long phys);
#endif /* __KERNEL__ */
#ifdef macintosh
#pragma options align=reset
#endif
#endif

19
include/asm-powerpc/btext.h
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@@ -7,21 +7,22 @@
#define __PPC_BTEXT_H
#ifdef __KERNEL__
extern void btext_clearscreen(void);
extern void btext_flushscreen(void);
extern int boot_text_mapped;
extern int btext_initialize(struct device_node *np);
extern void map_boot_text(void);
extern void init_boot_display(void);
extern int btext_find_display(int allow_nonstdout);
extern void btext_update_display(unsigned long phys, int width, int height,
int depth, int pitch);
extern void btext_setup_display(int width, int height, int depth, int pitch,
unsigned long address);
extern void btext_prepare_BAT(void);
extern void btext_unmap(void);
extern void btext_drawchar(char c);
extern void btext_drawstring(const char *str);
extern void btext_drawhex(unsigned long v);
extern void btext_drawtext(const char *c, unsigned int len);
extern void btext_clearscreen(void);
extern void btext_flushscreen(void);
extern void btext_flushline(void);
#endif /* __KERNEL__ */
#endif /* __PPC_BTEXT_H */

2
include/asm-powerpc/bug.h
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@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_BUG_H
#define _ASM_POWERPC_BUG_H
#ifdef __KERNEL__
#include <asm/asm-compat.h>
/*
@@ -67,4 +68,5 @@ struct bug_entry *find_bug(unsigned long bugaddr);
#include <asm-generic/bug.h>
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_BUG_H */

2
include/asm-powerpc/checksum.h
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@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_CHECKSUM_H
#define _ASM_POWERPC_CHECKSUM_H
#ifdef __KERNEL__
/*
* This program is free software; you can redistribute it and/or
@@ -129,4 +130,5 @@ static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
}
#endif
#endif /* __KERNEL__ */
#endif

2
include/asm-powerpc/compat.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_COMPAT_H
#define _ASM_POWERPC_COMPAT_H
#ifdef __KERNEL__
/*
* Architecture specific compatibility types
*/
@@ -202,4 +203,5 @@ struct compat_shmid64_ds {
compat_ulong_t __unused6;
};
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_COMPAT_H */

36
include/asm-powerpc/cputable.h
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@@ -1,7 +1,6 @@
#ifndef __ASM_POWERPC_CPUTABLE_H
#define __ASM_POWERPC_CPUTABLE_H
#include <linux/config.h>
#include <asm/asm-compat.h>
#define PPC_FEATURE_32 0x80000000
@@ -28,10 +27,17 @@
* via the mkdefs mechanism.
*/
struct cpu_spec;
struct op_powerpc_model;
typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
enum powerpc_oprofile_type {
INVALID = 0,
RS64 = 1,
POWER4 = 2,
G4 = 3,
BOOKE = 4,
};
struct cpu_spec {
/* CPU is matched via (PVR & pvr_mask) == pvr_value */
unsigned int pvr_mask;
@@ -57,7 +63,7 @@ struct cpu_spec {
char *oprofile_cpu_type;
/* Processor specific oprofile operations */
struct op_powerpc_model *oprofile_model;
enum powerpc_oprofile_type oprofile_type;
};
extern struct cpu_spec *cur_cpu_spec;
@@ -106,6 +112,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
#else
/* ensure on 32b processors the flags are available for compiling but
* don't do anything */
@@ -305,12 +312,18 @@ enum {
CPU_FTR_MMCRA_SIHV,
CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |
CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,
CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
#endif
CPU_FTRS_POSSIBLE =
#ifdef __powerpc64__
CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
CPU_FTR_CI_LARGE_PAGE |
#else
#if CLASSIC_PPC
CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
@@ -344,14 +357,14 @@ enum {
#ifdef CONFIG_E500
CPU_FTRS_E500 | CPU_FTRS_E500_2 |
#endif
#ifdef __powerpc64__
CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
CPU_FTR_CI_LARGE_PAGE |
#endif
#endif /* __powerpc64__ */
0,
CPU_FTRS_ALWAYS =
#ifdef __powerpc64__
CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
#else
#if CLASSIC_PPC
CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
@@ -385,10 +398,7 @@ enum {
#ifdef CONFIG_E500
CPU_FTRS_E500 & CPU_FTRS_E500_2 &
#endif
#ifdef __powerpc64__
CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
#endif
#endif /* __powerpc64__ */
CPU_FTRS_POSSIBLE,
};

2
include/asm-powerpc/current.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_CURRENT_H
#define _ASM_POWERPC_CURRENT_H
#ifdef __KERNEL__
/*
* This program is free software; you can redistribute it and/or
@@ -24,4 +25,5 @@ register struct task_struct *current asm ("r2");
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CURRENT_H */

2
include/asm-powerpc/delay.h
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@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_DELAY_H
#define _ASM_POWERPC_DELAY_H
#ifdef __KERNEL__
/*
* Copyright 1996, Paul Mackerras.
@@ -16,4 +17,5 @@
extern void __delay(unsigned long loops);
extern void udelay(unsigned long usecs);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_DELAY_H */

2
include/asm-powerpc/dma-mapping.h
View File

@@ -6,6 +6,7 @@
*/
#ifndef _ASM_DMA_MAPPING_H
#define _ASM_DMA_MAPPING_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/types.h>
@@ -282,4 +283,5 @@ struct dma_mapping_ops {
int (*dac_dma_supported)(struct device *dev, u64 mask);
};
#endif /* __KERNEL__ */
#endif /* _ASM_DMA_MAPPING_H */

2
include/asm-powerpc/dma.h
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@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_DMA_H
#define _ASM_POWERPC_DMA_H
#ifdef __KERNEL__
/*
* Defines for using and allocating dma channels.
@@ -387,4 +388,5 @@ extern int isa_dma_bridge_buggy;
#endif /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_DMA_H */

15
include/asm-powerpc/eeh.h
View File

@@ -19,6 +19,7 @@
#ifndef _PPC64_EEH_H
#define _PPC64_EEH_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/init.h>
@@ -57,6 +58,7 @@ void __init pci_addr_cache_build(void);
* to finish the eeh setup for this device.
*/
void eeh_add_device_early(struct device_node *);
void eeh_add_device_tree_early(struct device_node *);
void eeh_add_device_late(struct pci_dev *);
/**
@@ -71,6 +73,15 @@ void eeh_add_device_late(struct pci_dev *);
*/
void eeh_remove_device(struct pci_dev *);
/**
* eeh_remove_device_recursive - undo EEH for device & children.
* @dev: pci device to be removed
*
* As above, this removes the device; it also removes child
* pci devices as well.
*/
void eeh_remove_bus_device(struct pci_dev *);
/**
* EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
*
@@ -107,6 +118,9 @@ static inline void eeh_add_device_late(struct pci_dev *dev) { }
static inline void eeh_remove_device(struct pci_dev *dev) { }
static inline void eeh_add_device_tree_early(struct device_node *dn) { }
static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
#define EEH_POSSIBLE_ERROR(val, type) (0)
#define EEH_IO_ERROR_VALUE(size) (-1UL)
#endif /* CONFIG_EEH */
@@ -363,4 +377,5 @@ static inline void eeh_insl_ns(unsigned long port, void * buf, int nl)
eeh_check_failure((void __iomem *)(port), *(u32*)buf);
}
#endif /* __KERNEL__ */
#endif /* _PPC64_EEH_H */

2
include/asm-powerpc/eeh_event.h
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@@ -20,6 +20,7 @@
#ifndef ASM_PPC64_EEH_EVENT_H
#define ASM_PPC64_EEH_EVENT_H
#ifdef __KERNEL__
/** EEH event -- structure holding pci controller data that describes
* a change in the isolation status of a PCI slot. A pointer
@@ -49,4 +50,5 @@ int eeh_send_failure_event (struct device_node *dn,
int reset_state,
int time_unavail);
#endif /* __KERNEL__ */
#endif /* ASM_PPC64_EEH_EVENT_H */

3
include/asm-powerpc/elf.h
View File

@@ -1,7 +1,10 @@
#ifndef _ASM_POWERPC_ELF_H
#define _ASM_POWERPC_ELF_H
#ifdef __KERNEL__
#include <linux/sched.h> /* for task_struct */
#endif
#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/cputable.h>

6
include/asm-powerpc/firmware.h
View File

@@ -98,6 +98,12 @@ typedef struct {
extern firmware_feature_t firmware_features_table[];
#endif
extern void system_reset_fwnmi(void);
extern void machine_check_fwnmi(void);
/* This is true if we are using the firmware NMI handler (typically LPAR) */
extern int fwnmi_active;
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_POWERPC_FIRMWARE_H */

2
include/asm-powerpc/floppy.h
View File

@@ -9,6 +9,7 @@
*/
#ifndef __ASM_POWERPC_FLOPPY_H
#define __ASM_POWERPC_FLOPPY_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <asm/machdep.h>
@@ -102,4 +103,5 @@ static int FDC2 = -1;
#define EXTRA_FLOPPY_PARAMS
#endif /* __KERNEL__ */
#endif /* __ASM_POWERPC_FLOPPY_H */

5
include/asm-powerpc/grackle.h
View File

@@ -1,3 +1,6 @@
#ifndef _ASM_POWERPC_GRACKLE_H
#define _ASM_POWERPC_GRACKLE_H
#ifdef __KERNEL__
/*
* Functions for setting up and using a MPC106 northbridge
*/
@@ -5,3 +8,5 @@
#include <asm/pci-bridge.h>
extern void setup_grackle(struct pci_controller *hose);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_GRACKLE_H */

2
include/asm-powerpc/hardirq.h
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@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_HARDIRQ_H
#define _ASM_POWERPC_HARDIRQ_H
#ifdef __KERNEL__
#include <asm/irq.h>
#include <asm/bug.h>
@@ -24,4 +25,5 @@ static inline void ack_bad_irq(int irq)
BUG();
}
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_HARDIRQ_H */

5
include/asm-powerpc/heathrow.h
View File

@@ -1,3 +1,6 @@
#ifndef _ASM_POWERPC_HEATHROW_H
#define _ASM_POWERPC_HEATHROW_H
#ifdef __KERNEL__
/*
* heathrow.h: definitions for using the "Heathrow" I/O controller chip.
*
@@ -60,3 +63,5 @@
/* Looks like Heathrow has some sort of GPIOs as well... */
#define HRW_GPIO_MODEM_RESET 0x6d
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_HEATHROW_H */

2
include/asm-powerpc/hvcall.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_HVCALL_H
#define _ASM_POWERPC_HVCALL_H
#ifdef __KERNEL__
#define HVSC .long 0x44000022
@@ -170,4 +171,5 @@ long plpar_hcall_4out(unsigned long opcode,
unsigned long *out4);
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_HVCALL_H */

2
include/asm-powerpc/hvconsole.h
View File

@@ -21,6 +21,7 @@
#ifndef _PPC64_HVCONSOLE_H
#define _PPC64_HVCONSOLE_H
#ifdef __KERNEL__
/*
* This is the max number of console adapters that can/will be found as
@@ -46,4 +47,5 @@ extern struct hvc_struct * __devinit hvc_alloc(uint32_t vtermno, int irq,
struct hv_ops *ops);
/* remove a vterm from hvc tty operation (modele_exit or hotplug remove) */
extern int __devexit hvc_remove(struct hvc_struct *hp);
#endif /* __KERNEL__ */
#endif /* _PPC64_HVCONSOLE_H */

2
include/asm-powerpc/hvcserver.h
View File

@@ -21,6 +21,7 @@
#ifndef _PPC64_HVCSERVER_H
#define _PPC64_HVCSERVER_H
#ifdef __KERNEL__
#include <linux/list.h>
@@ -54,4 +55,5 @@ extern int hvcs_register_connection(uint32_t unit_address,
uint32_t p_partition_ID, uint32_t p_unit_address);
extern int hvcs_free_connection(uint32_t unit_address);
#endif /* __KERNEL__ */
#endif /* _PPC64_HVCSERVER_H */

2
include/asm-powerpc/i8259.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_I8259_H
#define _ASM_POWERPC_I8259_H
#ifdef __KERNEL__
#include <linux/irq.h>
@@ -9,4 +10,5 @@ extern void i8259_init(unsigned long intack_addr, int offset);
extern int i8259_irq(struct pt_regs *regs);
extern int i8259_irq_cascade(struct pt_regs *regs, void *unused);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_I8259_H */

85
include/asm-powerpc/ibmebus.h Normal file
View File

@@ -0,0 +1,85 @@
/*
* IBM PowerPC eBus Infrastructure Support.
*
* Copyright (c) 2005 IBM Corporation
* Heiko J Schick <schickhj@de.ibm.com>
*
* All rights reserved.
*
* This source code is distributed under a dual license of GPL v2.0 and OpenIB
* BSD.
*
* OpenIB BSD License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ASM_EBUS_H
#define _ASM_EBUS_H
#ifdef __KERNEL__
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/mod_devicetable.h>
#include <asm/of_device.h>
extern struct dma_mapping_ops ibmebus_dma_ops;
extern struct bus_type ibmebus_bus_type;
struct ibmebus_dev {
char *name;
struct of_device ofdev;
};
struct ibmebus_driver {
char *name;
struct of_device_id *id_table;
int (*probe) (struct ibmebus_dev *dev, const struct of_device_id *id);
int (*remove) (struct ibmebus_dev *dev);
struct device_driver driver;
};
int ibmebus_register_driver(struct ibmebus_driver *drv);
void ibmebus_unregister_driver(struct ibmebus_driver *drv);
int ibmebus_request_irq(struct ibmebus_dev *dev,
u32 ist,
irqreturn_t (*handler)(int, void*, struct pt_regs *),
unsigned long irq_flags, const char * devname,
void *dev_id);
void ibmebus_free_irq(struct ibmebus_dev *dev, u32 ist, void *dev_id);
static inline struct ibmebus_driver *to_ibmebus_driver(struct device_driver *drv)
{
return container_of(drv, struct ibmebus_driver, driver);
}
static inline struct ibmebus_dev *to_ibmebus_dev(struct device *dev)
{
return container_of(dev, struct ibmebus_dev, ofdev.dev);
}
#endif /* __KERNEL__ */
#endif /* _ASM_IBMEBUS_H */

6
include/asm-powerpc/io.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_IO_H
#define _ASM_POWERPC_IO_H
#ifdef __KERNEL__
/*
* This program is free software; you can redistribute it and/or
@@ -186,7 +187,6 @@ extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
#define IO_SPACE_LIMIT ~(0UL)
#ifdef __KERNEL__
extern int __ioremap_explicit(unsigned long p_addr, unsigned long v_addr,
unsigned long size, unsigned long flags);
extern void __iomem *__ioremap(unsigned long address, unsigned long size,
@@ -256,8 +256,6 @@ static inline void * phys_to_virt(unsigned long address)
*/
#define BIO_VMERGE_BOUNDARY 0
#endif /* __KERNEL__ */
static inline void iosync(void)
{
__asm__ __volatile__ ("sync" : : : "memory");
@@ -405,8 +403,6 @@ static inline void out_be64(volatile unsigned long __iomem *addr, unsigned long
#include <asm/eeh.h>
#endif
#ifdef __KERNEL__
/**
* check_signature - find BIOS signatures
* @io_addr: mmio address to check

8
include/asm-powerpc/iommu.h
View File

@@ -20,6 +20,7 @@
#ifndef _ASM_IOMMU_H
#define _ASM_IOMMU_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <asm/types.h>
@@ -56,7 +57,7 @@ struct device_node;
/* Walks all buses and creates iommu tables */
extern void iommu_setup_pSeries(void);
extern void iommu_setup_u3(void);
extern void iommu_setup_dart(void);
/* Frees table for an individual device node */
extern void iommu_free_table(struct device_node *dn);
@@ -104,7 +105,7 @@ extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
extern void iommu_init_early_pSeries(void);
extern void iommu_init_early_iSeries(void);
extern void iommu_init_early_u3(void);
extern void iommu_init_early_dart(void);
#ifdef CONFIG_PCI
extern void pci_iommu_init(void);
@@ -113,6 +114,7 @@ extern void pci_direct_iommu_init(void);
static inline void pci_iommu_init(void) { }
#endif
extern void alloc_u3_dart_table(void);
extern void alloc_dart_table(void);
#endif /* __KERNEL__ */
#endif /* _ASM_IOMMU_H */

85
include/asm-powerpc/ipic.h Normal file
View File

@@ -0,0 +1,85 @@
/*
* include/asm-ppc/ipic.h
*
* IPIC external definitions and structure.
*
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
*
* Copyright 2005 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifdef __KERNEL__
#ifndef __ASM_IPIC_H__
#define __ASM_IPIC_H__
#include <linux/irq.h>
/* Flags when we init the IPIC */
#define IPIC_SPREADMODE_GRP_A 0x00000001
#define IPIC_SPREADMODE_GRP_D 0x00000002
#define IPIC_SPREADMODE_MIX_A 0x00000004
#define IPIC_SPREADMODE_MIX_B 0x00000008
#define IPIC_DISABLE_MCP_OUT 0x00000010
#define IPIC_IRQ0_MCP 0x00000020
/* IPIC registers offsets */
#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
#define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */
#define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
#define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
#define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
#define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
#define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
#define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
#define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
#define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
#define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
#define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
#define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */
#define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */
#define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
#define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
#define IPIC_SERSR 0x40 /* System Error Status Register */
#define IPIC_SERMR 0x44 /* System Error Mask Register */
#define IPIC_SERCR 0x48 /* System Error Control Register */
#define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */
#define IPIC_SIFCR_L 0x54 /* System Internal Interrupt Force Register (LOW) */
#define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
#define IPIC_SERFR 0x5C /* System Error Force Register */
#define IPIC_SCVCR 0x60 /* System Critical Interrupt Vector Register */
#define IPIC_SMVCR 0x64 /* System Management Interrupt Vector Register */
enum ipic_prio_grp {
IPIC_INT_GRP_A = IPIC_SIPRR_A,
IPIC_INT_GRP_D = IPIC_SIPRR_D,
IPIC_MIX_GRP_A = IPIC_SMPRR_A,
IPIC_MIX_GRP_B = IPIC_SMPRR_B,
};
enum ipic_mcp_irq {
IPIC_MCP_IRQ0 = 0,
IPIC_MCP_WDT = 1,
IPIC_MCP_SBA = 2,
IPIC_MCP_PCI1 = 5,
IPIC_MCP_PCI2 = 6,
IPIC_MCP_MU = 7,
};
extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
unsigned int irq_offset,
unsigned char *senses, unsigned int senses_count);
extern int ipic_set_priority(unsigned int irq, unsigned int priority);
extern void ipic_set_highest_priority(unsigned int irq);
extern void ipic_set_default_priority(void);
extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
extern u32 ipic_get_mcp_status(void);
extern void ipic_clear_mcp_status(u32 mask);
extern int ipic_get_irq(struct pt_regs *regs);
#endif /* __ASM_IPIC_H__ */
#endif /* __KERNEL__ */

2
include/asm-powerpc/iseries/it_lp_reg_save.h
View File

@@ -81,4 +81,6 @@ struct ItLpRegSave {
u8 xRsvd3[176]; // Reserved 350-3FF
};
extern struct ItLpRegSave iseries_reg_save[];
#endif /* _ITLPREGSAVE_H */

2
include/asm-powerpc/kdebug.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_KDEBUG_H
#define _ASM_POWERPC_KDEBUG_H
#ifdef __KERNEL__
/* nearly identical to x86_64/i386 code */
@@ -39,4 +40,5 @@ static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,lon
return notifier_call_chain(&powerpc_die_chain, val, &args);
}
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_KDEBUG_H */

13
include/asm-powerpc/kdump.h Normal file
View File

@@ -0,0 +1,13 @@
#ifndef _PPC64_KDUMP_H
#define _PPC64_KDUMP_H
/* How many bytes to reserve at zero for kdump. The reserve limit should
* be greater or equal to the trampoline's end address. */
#define KDUMP_RESERVE_LIMIT 0x8000
#define KDUMP_TRAMPOLINE_START 0x0100
#define KDUMP_TRAMPOLINE_END 0x3000
extern void kdump_setup(void);
#endif /* __PPC64_KDUMP_H */

19
include/asm-powerpc/kexec.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_KEXEC_H
#define _ASM_POWERPC_KEXEC_H
#ifdef __KERNEL__
/*
* Maximum page that is mapped directly into kernel memory.
@@ -30,8 +31,12 @@
#define KEXEC_ARCH KEXEC_ARCH_PPC
#endif
#define HAVE_ARCH_COPY_OLDMEM_PAGE
#ifndef __ASSEMBLY__
#ifdef CONFIG_KEXEC
#define MAX_NOTE_BYTES 1024
typedef u32 note_buf_t[MAX_NOTE_BYTES / sizeof(u32)];
@@ -41,10 +46,18 @@ extern note_buf_t crash_notes[];
extern void kexec_smp_wait(void); /* get and clear naca physid, wait for
master to copy new code to 0 */
extern void __init kexec_setup(void);
#else
extern int crashing_cpu;
extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
#endif /* __powerpc64 __ */
struct kimage;
extern void machine_kexec_simple(struct kimage *image);
#endif
struct pt_regs;
extern void default_machine_kexec(struct kimage *image);
extern int default_machine_kexec_prepare(struct kimage *image);
extern void default_machine_crash_shutdown(struct pt_regs *regs);
#endif /* !CONFIG_KEXEC */
#endif /* ! __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_KEXEC_H */

15
include/asm-powerpc/keylargo.h
View File

@@ -1,3 +1,6 @@
#ifndef _ASM_POWERPC_KEYLARGO_H
#define _ASM_POWERPC_KEYLARGO_H
#ifdef __KERNEL__
/*
* keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
*
@@ -232,10 +235,12 @@
#define K2_FCR1_I2S0_RESET 0x00000800
#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
#define K2_FCR1_I2S0_ENABLE 0x00002000
#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
#define K2_FCR1_FW_CLK_ENABLE 0x00008000
#define K2_FCR1_FW_RESET_N 0x00010000
#define K2_FCR1_I2S1_CELL_ENABLE 0x00020000
#define K2_FCR1_I2S1_CLK_ENABLE_BIT 0x00080000
#define K2_FCR1_I2S1_ENABLE 0x00100000
#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
#define K2_FCR1_GMAC_RESET_N 0x01000000
@@ -246,3 +251,11 @@
#define K2_FCR1_UATA_RESET_N 0x40000000
#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
/* Shasta definitions */
#define SH_FCR1_I2S2_CELL_ENABLE 0x00000010
#define SH_FCR1_I2S2_CLK_ENABLE_BIT 0x00000040
#define SH_FCR1_I2S2_ENABLE 0x00000080
#define SH_FCR3_I2S2_CLK18_ENABLE 0x00008000
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_KEYLARGO_H */

2
include/asm-powerpc/kprobes.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_KPROBES_H
#define _ASM_POWERPC_KPROBES_H
#ifdef __KERNEL__
/*
* Kernel Probes (KProbes)
*
@@ -78,4 +79,5 @@ static inline int kprobe_exceptions_notify(struct notifier_block *self,
return 0;
}
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_KPROBES_H */

2
include/asm-powerpc/lmb.h
View File

@@ -1,5 +1,6 @@
#ifndef _PPC64_LMB_H
#define _PPC64_LMB_H
#ifdef __KERNEL__
/*
* Definitions for talking to the Open Firmware PROM on
@@ -78,4 +79,5 @@ lmb_end_pfn(struct lmb_region *type, unsigned long region_nr)
lmb_size_pages(type, region_nr);
}
#endif /* __KERNEL__ */
#endif /* _PPC64_LMB_H */

2
include/asm-powerpc/lppaca.h
View File

@@ -18,6 +18,7 @@
*/
#ifndef _ASM_POWERPC_LPPACA_H
#define _ASM_POWERPC_LPPACA_H
#ifdef __KERNEL__
//=============================================================================
//
@@ -128,4 +129,5 @@ struct lppaca {
u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF
};
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_LPPACA_H */

12
include/asm-powerpc/machdep.h
View File

@@ -27,6 +27,9 @@ struct device_node;
struct iommu_table;
struct rtc_time;
struct file;
#ifdef CONFIG_KEXEC
struct kimage;
#endif
#ifdef CONFIG_SMP
struct smp_ops_t {
@@ -131,7 +134,7 @@ struct machdep_calls {
void (*nvram_sync)(void);
/* Exception handlers */
void (*system_reset_exception)(struct pt_regs *regs);
int (*system_reset_exception)(struct pt_regs *regs);
int (*machine_check_exception)(struct pt_regs *regs);
/* Motherboard/chipset features. This is a kind of general purpose
@@ -207,19 +210,19 @@ struct machdep_calls {
/* this is for modules, since _machine can be a define -- Cort */
int ppc_machine;
#endif /* CONFIG_PPC32 */
#ifdef CONFIG_KEXEC
/* Called to shutdown machine specific hardware not already controlled
* by other drivers.
* XXX Should we move this one out of kexec scope?
*/
void (*machine_shutdown)(void);
#ifdef CONFIG_KEXEC
/* Called to do the minimal shutdown needed to run a kexec'd kernel
* to run successfully.
* XXX Should we move this one out of kexec scope?
*/
void (*machine_crash_shutdown)(void);
void (*machine_crash_shutdown)(struct pt_regs *regs);
/* Called to do what every setup is needed on image and the
* reboot code buffer. Returns 0 on success.
@@ -237,7 +240,6 @@ struct machdep_calls {
*/
void (*machine_kexec)(struct kimage *image);
#endif /* CONFIG_KEXEC */
#endif /* CONFIG_PPC32 */
};
extern void default_idle(void);

2
include/asm-powerpc/macio.h
View File

@@ -1,5 +1,6 @@
#ifndef __MACIO_ASIC_H__
#define __MACIO_ASIC_H__
#ifdef __KERNEL__
#include <asm/of_device.h>
@@ -137,4 +138,5 @@ struct macio_driver
extern int macio_register_driver(struct macio_driver *);
extern void macio_unregister_driver(struct macio_driver *);
#endif /* __KERNEL__ */
#endif /* __MACIO_ASIC_H__ */

9
include/asm-powerpc/mmu.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_MMU_H_
#define _ASM_POWERPC_MMU_H_
#ifdef __KERNEL__
#ifndef CONFIG_PPC64
#include <asm-ppc/mmu.h>
@@ -33,7 +34,8 @@
/* Location of cpu0's segment table */
#define STAB0_PAGE 0x6
#define STAB0_PHYS_ADDR (STAB0_PAGE<<12)
#define STAB0_OFFSET (STAB0_PAGE << 12)
#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
#ifndef __ASSEMBLY__
extern char initial_stab[];
@@ -394,7 +396,12 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
/* Physical address used by some IO functions */
typedef unsigned long phys_addr_t;
#endif /* __ASSEMBLY */
#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */

2
include/asm-powerpc/mmu_context.h
View File

@@ -1,5 +1,6 @@
#ifndef __ASM_POWERPC_MMU_CONTEXT_H
#define __ASM_POWERPC_MMU_CONTEXT_H
#ifdef __KERNEL__
#ifndef CONFIG_PPC64
#include <asm-ppc/mmu_context.h>
@@ -86,4 +87,5 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
}
#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* __ASM_POWERPC_MMU_CONTEXT_H */

2
include/asm-powerpc/mmzone.h
View File

@@ -6,6 +6,7 @@
*/
#ifndef _ASM_MMZONE_H_
#define _ASM_MMZONE_H_
#ifdef __KERNEL__
#include <linux/config.h>
@@ -47,4 +48,5 @@ extern unsigned long max_pfn;
extern int __init early_pfn_to_nid(unsigned long pfn);
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_MMZONE_H_ */

2
include/asm-powerpc/module.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_MODULE_H
#define _ASM_POWERPC_MODULE_H
#ifdef __KERNEL__
/*
* This program is free software; you can redistribute it and/or
@@ -74,4 +75,5 @@ struct exception_table_entry;
void sort_ex_table(struct exception_table_entry *start,
struct exception_table_entry *finish);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MODULE_H */

6
include/asm-powerpc/mpic.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_MPIC_H
#define _ASM_POWERPC_MPIC_H
#ifdef __KERNEL__
#include <linux/irq.h>
@@ -117,7 +118,9 @@ typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
struct mpic_irq_fixup
{
u8 __iomem *base;
unsigned int irq;
u8 __iomem *applebase;
u32 data;
unsigned int index;
};
#endif /* CONFIG_MPIC_BROKEN_U3 */
@@ -284,4 +287,5 @@ extern int mpic_get_irq(struct pt_regs *regs);
/* global mpic for pSeries */
extern struct mpic *pSeries_mpic;
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MPIC_H */

2
include/asm-powerpc/numnodes.h
View File

@@ -1,7 +1,9 @@
#ifndef _ASM_POWERPC_MAX_NUMNODES_H
#define _ASM_POWERPC_MAX_NUMNODES_H
#ifdef __KERNEL__
/* Max 16 Nodes */
#define NODES_SHIFT 4
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MAX_NUMNODES_H */

4
include/asm-powerpc/nvram.h
View File

@@ -55,6 +55,7 @@ struct nvram_header {
char name[12];
};
#ifdef __KERNEL__
struct nvram_partition {
struct list_head partition;
struct nvram_header header;
@@ -69,6 +70,7 @@ extern struct nvram_partition *nvram_find_partition(int sig, const char *name);
extern int pSeries_nvram_init(void);
extern int mmio_nvram_init(void);
#endif /* __KERNEL__ */
/* PowerMac specific nvram stuffs */
@@ -78,6 +80,7 @@ enum {
pmac_nvram_NR /* MacOS Name Registry partition */
};
#ifdef __KERNEL__
/* Return partition offset in nvram */
extern int pmac_get_partition(int partition);
@@ -91,6 +94,7 @@ extern void nvram_sync(void);
/* Normal access to NVRAM */
extern unsigned char nvram_read_byte(int i);
extern void nvram_write_byte(unsigned char c, int i);
#endif
/* Some offsets in XPRAM */
#define PMAC_XPRAM_MACHINE_LOC 0xe4

2
include/asm-powerpc/of_device.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_OF_DEVICE_H
#define _ASM_POWERPC_OF_DEVICE_H
#ifdef __KERNEL__
#include <linux/device.h>
#include <linux/mod_devicetable.h>
@@ -61,4 +62,5 @@ extern struct of_device *of_platform_device_create(struct device_node *np,
struct device *parent);
extern void of_release_dev(struct device *dev);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_OF_DEVICE_H */

6
include/asm-powerpc/ohare.h
View File

@@ -1,3 +1,6 @@
#ifndef _ASM_POWERPC_OHARE_H
#define _ASM_POWERPC_OHARE_H
#ifdef __KERNEL__
/*
* ohare.h: definitions for using the "O'Hare" I/O controller chip.
*
@@ -46,3 +49,6 @@
* Contributed by Harry Eaton.
*/
#define STARMAX_FEATURES 0xbeff7a
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_OHARE_H */

33
include/asm-powerpc/oprofile_impl.h
View File

@@ -11,6 +11,7 @@
#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
#define _ASM_POWERPC_OPROFILE_IMPL_H
#ifdef __KERNEL__
#define OP_MAX_COUNTER 8
@@ -22,24 +23,22 @@ struct op_counter_config {
unsigned long enabled;
unsigned long event;
unsigned long count;
/* Classic doesn't support per-counter user/kernel selection */
unsigned long kernel;
#ifdef __powerpc64__
/* We dont support per counter user/kernel selection */
#endif
unsigned long user;
unsigned long unit_mask;
};
/* System-wide configuration as set via oprofilefs. */
struct op_system_config {
#ifdef __powerpc64__
#ifdef CONFIG_PPC64
unsigned long mmcr0;
unsigned long mmcr1;
unsigned long mmcra;
#endif
unsigned long enable_kernel;
unsigned long enable_user;
#ifdef __powerpc64__
#ifdef CONFIG_PPC64
unsigned long backtrace_spinlocks;
#endif
};
@@ -49,9 +48,7 @@ struct op_powerpc_model {
void (*reg_setup) (struct op_counter_config *,
struct op_system_config *,
int num_counters);
#ifdef __powerpc64__
void (*cpu_setup) (void *);
#endif
void (*start) (struct op_counter_config *);
void (*stop) (void);
void (*handle_interrupt) (struct pt_regs *,
@@ -59,10 +56,19 @@ struct op_powerpc_model {
int num_counters;
};
#ifdef __powerpc64__
#ifdef CONFIG_FSL_BOOKE
extern struct op_powerpc_model op_model_fsl_booke;
#else /* Otherwise, it's classic */
#ifdef CONFIG_PPC64
extern struct op_powerpc_model op_model_rs64;
extern struct op_powerpc_model op_model_power4;
#else /* Otherwise, CONFIG_PPC32 */
extern struct op_powerpc_model op_model_7450;
#endif
/* All the classic PPC parts use these */
static inline unsigned int ctr_read(unsigned int i)
{
switch(i) {
@@ -78,10 +84,14 @@ static inline unsigned int ctr_read(unsigned int i)
return mfspr(SPRN_PMC5);
case 5:
return mfspr(SPRN_PMC6);
/* No PPC32 chip has more than 6 so far */
#ifdef CONFIG_PPC64
case 6:
return mfspr(SPRN_PMC7);
case 7:
return mfspr(SPRN_PMC8);
#endif
default:
return 0;
}
@@ -108,16 +118,21 @@ static inline void ctr_write(unsigned int i, unsigned int val)
case 5:
mtspr(SPRN_PMC6, val);
break;
/* No PPC32 chip has more than 6, yet */
#ifdef CONFIG_PPC64
case 6:
mtspr(SPRN_PMC7, val);
break;
case 7:
mtspr(SPRN_PMC8, val);
break;
#endif
default:
break;
}
}
#endif /* __powerpc64__ */
#endif /* !CONFIG_FSL_BOOKE */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */

2
include/asm-powerpc/pSeries_reconfig.h
View File

@@ -1,5 +1,6 @@
#ifndef _PPC64_PSERIES_RECONFIG_H
#define _PPC64_PSERIES_RECONFIG_H
#ifdef __KERNEL__
#include <linux/notifier.h>
@@ -22,4 +23,5 @@ static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
#endif /* CONFIG_PPC_PSERIES */
#endif /* __KERNEL__ */
#endif /* _PPC64_PSERIES_RECONFIG_H */

21
include/asm-powerpc/paca.h
View File

@@ -14,11 +14,11 @@
*/
#ifndef _ASM_POWERPC_PACA_H
#define _ASM_POWERPC_PACA_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <asm/types.h>
#include <asm/lppaca.h>
#include <asm/iseries/it_lp_reg_save.h>
#include <asm/mmu.h>
register struct paca_struct *local_paca asm("r13");
@@ -31,9 +31,9 @@ struct task_struct;
*
* This structure is not directly accessed by firmware or the service
* processor except for the first two pointers that point to the
* lppaca area and the ItLpRegSave area for this CPU. Both the
* lppaca and ItLpRegSave objects are currently contained within the
* PACA but they do not need to be.
* lppaca area and the ItLpRegSave area for this CPU. The lppaca
* object is currently contained within the PACA but it doesn't need
* to be.
*/
struct paca_struct {
/*
@@ -48,7 +48,9 @@ struct paca_struct {
* accessed by the firmware
*/
struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
struct ItLpRegSave *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
#ifdef CONFIG_PPC_ISERIES
void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
#endif /* CONFIG_PPC_ISERIES */
/*
* MAGIC: the spinlock functions in arch/ppc64/lib/locks.c
@@ -59,7 +61,6 @@ struct paca_struct {
u16 lock_token; /* Constant 0x8000, used in locks */
u16 paca_index; /* Logical processor number */
u32 default_decr; /* Default decrementer value */
u64 kernel_toc; /* Kernel TOC address */
u64 stab_real; /* Absolute address of segment table */
u64 stab_addr; /* Virtual address of segment table */
@@ -90,14 +91,10 @@ struct paca_struct {
struct task_struct *__current; /* Pointer to current */
u64 kstack; /* Saved Kernel stack addr */
u64 stab_rr; /* stab/slb round-robin counter */
u64 next_jiffy_update_tb; /* TB value for next jiffy update */
u64 saved_r1; /* r1 save for RTAS calls */
u64 saved_msr; /* MSR saved here by enter_rtas */
u8 proc_enabled; /* irq soft-enable flag */
/* not yet used */
u64 exdsi[8]; /* used for linear mapping hash table misses */
/*
* iSeries structure which the hypervisor knows about -
* this structure should not cross a page boundary.
@@ -110,11 +107,9 @@ struct paca_struct {
* cross a page boundary.
*/
struct lppaca lppaca __attribute__((__aligned__(0x400)));
#ifdef CONFIG_PPC_ISERIES
struct ItLpRegSave reg_save;
#endif
};
extern struct paca_struct paca[];
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PACA_H */

32
include/asm-powerpc/page.h
View File

@@ -37,8 +37,30 @@
*/
#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
/*
* KERNELBASE is the virtual address of the start of the kernel, it's often
* the same as PAGE_OFFSET, but _might not be_.
*
* The kdump dump kernel is one example where KERNELBASE != PAGE_OFFSET.
*
* To get a physical address from a virtual one you subtract PAGE_OFFSET,
* _not_ KERNELBASE.
*
* If you want to know something's offset from the start of the kernel you
* should subtract KERNELBASE.
*
* If you want to test if something's a kernel address, use is_kernel_addr().
*/
#ifdef CONFIG_CRASH_DUMP
/* Kdump kernel runs at 32 MB, change at your peril. */
#define PHYSICAL_START 0x2000000
#else
#define PHYSICAL_START 0x0
#endif
#define PAGE_OFFSET ASM_CONST(CONFIG_KERNEL_START)
#define KERNELBASE PAGE_OFFSET
#define KERNELBASE (PAGE_OFFSET + PHYSICAL_START)
#ifdef CONFIG_DISCONTIGMEM
#define page_to_pfn(page) discontigmem_page_to_pfn(page)
@@ -56,7 +78,7 @@
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
#define __va(x) ((void *)((unsigned long)(x) + KERNELBASE))
#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
/*
@@ -86,6 +108,12 @@
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE)
/*
* Don't compare things with KERNELBASE or PAGE_OFFSET to test for
* "kernelness", use is_kernel_addr() - it should do what you want.
*/
#define is_kernel_addr(x) ((x) >= PAGE_OFFSET)
#ifndef __ASSEMBLY__
#undef STRICT_MM_TYPECHECKS

2
include/asm-powerpc/page_32.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_PAGE_32_H
#define _ASM_POWERPC_PAGE_32_H
#ifdef __KERNEL__
#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
@@ -37,4 +38,5 @@ extern __inline__ int get_order(unsigned long size)
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PAGE_32_H */

12
include/asm-powerpc/page_64.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_PAGE_64_H
#define _ASM_POWERPC_PAGE_64_H
#ifdef __KERNEL__
/*
* Copyright (C) 2001 PPC64 Team, IBM Corp
@@ -25,16 +26,6 @@
*/
#define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT)
#define REGION_SIZE 4UL
#define REGION_SHIFT 60UL
#define REGION_MASK (((1UL<<REGION_SIZE)-1UL)<<REGION_SHIFT)
#define VMALLOCBASE ASM_CONST(0xD000000000000000)
#define VMALLOC_REGION_ID (VMALLOCBASE >> REGION_SHIFT)
#define KERNEL_REGION_ID (KERNELBASE >> REGION_SHIFT)
#define USER_REGION_ID (0UL)
#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
/* Segment size */
#define SID_SHIFT 28
#define SID_MASK 0xfffffffffUL
@@ -180,4 +171,5 @@ extern unsigned int HPAGE_SHIFT;
#include <asm-generic/page.h>
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PAGE_64_H */

2
include/asm-powerpc/param.h
View File

@@ -1,8 +1,6 @@
#ifndef _ASM_POWERPC_PARAM_H
#define _ASM_POWERPC_PARAM_H
#include <linux/config.h>
#ifdef __KERNEL__
#define HZ CONFIG_HZ /* internal kernel timer frequency */
#define USER_HZ 100 /* for user interfaces in "ticks" */

2
include/asm-powerpc/parport.h
View File

@@ -8,6 +8,7 @@
#ifndef _ASM_POWERPC_PARPORT_H
#define _ASM_POWERPC_PARPORT_H
#ifdef __KERNEL__
static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
@@ -15,4 +16,5 @@ static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
return parport_pc_find_isa_ports (autoirq, autodma);
}
#endif /* __KERNEL__ */
#endif /* !(_ASM_POWERPC_PARPORT_H) */

24
include/asm-powerpc/pci-bridge.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
#ifndef CONFIG_PPC64
#include <asm-ppc/pci-bridge.h>
@@ -125,9 +126,19 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
return bus->sysdata; /* Must be root bus (PHB) */
}
/** Find the bus corresponding to the indicated device node */
struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
struct device_node *dev, int primary);
/** Remove all of the PCI devices under this bus */
void pcibios_remove_pci_devices(struct pci_bus *bus);
/** Discover new pci devices under this bus, and add them */
void pcibios_add_pci_devices(struct pci_bus * bus);
void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
extern int pcibios_remove_root_bus(struct pci_controller *phb);
extern void phbs_remap_io(void);
@@ -140,14 +151,27 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
return PCI_DN(busdn)->phb;
}
extern struct pci_controller*
pci_find_hose_for_OF_device(struct device_node* node);
extern struct pci_controller *
pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
#ifdef CONFIG_PCI
extern unsigned long pci_address_to_pio(phys_addr_t address);
#else
static inline unsigned long pci_address_to_pio(phys_addr_t address)
{
return (unsigned long)-1;
}
#endif
/* Return values for ppc_md.pci_probe_mode function */
#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif

2
include/asm-powerpc/pci.h
View File

@@ -216,6 +216,8 @@ extern int remap_bus_range(struct pci_bus *bus);
extern void pcibios_fixup_device_resources(struct pci_dev *dev,
struct pci_bus *bus);
extern void pcibios_claim_one_bus(struct pci_bus *b);
extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
extern struct pci_dev *of_create_pci_dev(struct device_node *node,

2
include/asm-powerpc/pgalloc.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_PGALLOC_H
#define _ASM_POWERPC_PGALLOC_H
#ifdef __KERNEL__
#ifndef CONFIG_PPC64
#include <asm-ppc/pgalloc.h>
@@ -153,4 +154,5 @@ extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
#define check_pgt_cache() do { } while (0)
#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PGALLOC_H */

6
include/asm-powerpc/pgtable-64k.h
View File

@@ -1,3 +1,7 @@
#ifndef _ASM_POWERPC_PGTABLE_64K_H
#define _ASM_POWERPC_PGTABLE_64K_H
#ifdef __KERNEL__
#include <asm-generic/pgtable-nopud.h>
@@ -88,3 +92,5 @@
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PGTABLE_64K_H */

13
include/asm-powerpc/pgtable.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_PGTABLE_H
#define _ASM_POWERPC_PGTABLE_H
#ifdef __KERNEL__
#ifndef CONFIG_PPC64
#include <asm-ppc/pgtable.h>
@@ -57,6 +58,17 @@ struct mm_struct;
#define IMALLOC_BASE (PHBS_IO_BASE + 0x80000000ul) /* Reserve 2 gigs for PHBs */
#define IMALLOC_END (VMALLOC_START + PGTABLE_RANGE)
/*
* Region IDs
*/
#define REGION_SHIFT 60UL
#define REGION_MASK (0xfUL << REGION_SHIFT)
#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
#define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START))
#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
#define USER_REGION_ID (0UL)
/*
* Common bits in a linux-style PTE. These match the bits in the
* (hardware-defined) PowerPC PTE as closely as possible. Additional
@@ -521,4 +533,5 @@ void pgtable_cache_init(void);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PGTABLE_H */

25
include/asm-powerpc/pmac_feature.h
View File

@@ -121,6 +121,7 @@
#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */
#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */
#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */
#define PMAC_TYPE_UNKNOWN_SHASTA 0x19e /* Any other Shasta based */
/*
* Motherboard flags
@@ -317,10 +318,6 @@ extern void pmac_register_agp_pm(struct pci_dev *bridge,
extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
extern void pmac_resume_agp_for_card(struct pci_dev *dev);
/* Used by the via-pmu driver for suspend/resume
*/
extern void pmac_tweak_clock_spreading(int enable);
/*
* The part below is for use by macio_asic.c only, do not rely
* on the data structures or constants below in a normal driver
@@ -341,6 +338,7 @@ enum {
macio_pangea,
macio_intrepid,
macio_keylargo2,
macio_shasta,
};
struct macio_chip
@@ -376,5 +374,24 @@ extern struct macio_chip* macio_find(struct device_node* child, int type);
#define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r)))
#define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v)))
/*
* Those are exported by pmac feature for internal use by arch code
* only like the platform function callbacks, do not use directly in drivers
*/
extern spinlock_t feature_lock;
extern struct device_node *uninorth_node;
extern u32 __iomem *uninorth_base;
/*
* Uninorth reg. access. Note that Uni-N regs are big endian
*/
#define UN_REG(r) (uninorth_base + ((r) >> 2))
#define UN_IN(r) (in_be32(UN_REG(r)))
#define UN_OUT(r,v) (out_be32(UN_REG(r), (v)))
#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
#endif /* __PPC_ASM_PMAC_FEATURE_H */
#endif /* __KERNEL__ */

94
include/asm-powerpc/pmac_low_i2c.h
View File

@@ -11,33 +11,97 @@
*/
#ifndef __PMAC_LOW_I2C_H__
#define __PMAC_LOW_I2C_H__
#ifdef __KERNEL__
/* i2c mode (based on the platform functions format) */
enum {
pmac_low_i2c_mode_dumb = 1,
pmac_low_i2c_mode_std = 2,
pmac_low_i2c_mode_stdsub = 3,
pmac_low_i2c_mode_combined = 4,
pmac_i2c_mode_dumb = 1,
pmac_i2c_mode_std = 2,
pmac_i2c_mode_stdsub = 3,
pmac_i2c_mode_combined = 4,
};
/* RW bit in address */
enum {
pmac_low_i2c_read = 0x01,
pmac_low_i2c_write = 0x00
pmac_i2c_read = 0x01,
pmac_i2c_write = 0x00
};
/* Init, called early during boot */
extern void pmac_init_low_i2c(void);
/* i2c bus type */
enum {
pmac_i2c_bus_keywest = 0,
pmac_i2c_bus_pmu = 1,
pmac_i2c_bus_smu = 2,
};
/* Locking functions exposed to i2c-keywest */
int pmac_low_i2c_lock(struct device_node *np);
int pmac_low_i2c_unlock(struct device_node *np);
/* i2c bus features */
enum {
/* can_largesub : supports >1 byte subaddresses (SMU only) */
pmac_i2c_can_largesub = 0x00000001u,
/* multibus : device node holds multiple busses, bus number is
* encoded in bits 0xff00 of "reg" of a given device
*/
pmac_i2c_multibus = 0x00000002u,
};
/* i2c busses in the system */
struct pmac_i2c_bus;
struct i2c_adapter;
/* Init, called early during boot */
extern int pmac_i2c_init(void);
/* Lookup an i2c bus for a device-node. The node can be either the bus
* node itself or a device below it. In the case of a multibus, the bus
* node itself is the controller node, else, it's a child of the controller
* node
*/
extern struct pmac_i2c_bus *pmac_i2c_find_bus(struct device_node *node);
/* Get the address for an i2c device. This strips the bus number if
* necessary. The 7 bits address is returned 1 bit right shifted so that the
* direction can be directly ored in
*/
extern u8 pmac_i2c_get_dev_addr(struct device_node *device);
/* Get infos about a bus */
extern struct device_node *pmac_i2c_get_controller(struct pmac_i2c_bus *bus);
extern struct device_node *pmac_i2c_get_bus_node(struct pmac_i2c_bus *bus);
extern int pmac_i2c_get_type(struct pmac_i2c_bus *bus);
extern int pmac_i2c_get_flags(struct pmac_i2c_bus *bus);
extern int pmac_i2c_get_channel(struct pmac_i2c_bus *bus);
/* i2c layer adapter attach/detach */
extern void pmac_i2c_attach_adapter(struct pmac_i2c_bus *bus,
struct i2c_adapter *adapter);
extern void pmac_i2c_detach_adapter(struct pmac_i2c_bus *bus,
struct i2c_adapter *adapter);
extern struct i2c_adapter *pmac_i2c_get_adapter(struct pmac_i2c_bus *bus);
extern struct pmac_i2c_bus *pmac_i2c_adapter_to_bus(struct i2c_adapter *adapter);
/* March a device or bus with an i2c adapter structure, to be used by drivers
* to match device-tree nodes with i2c adapters during adapter discovery
* callbacks
*/
extern int pmac_i2c_match_adapter(struct device_node *dev,
struct i2c_adapter *adapter);
/* (legacy) Locking functions exposed to i2c-keywest */
extern int pmac_low_i2c_lock(struct device_node *np);
extern int pmac_low_i2c_unlock(struct device_node *np);
/* Access functions for platform code */
int pmac_low_i2c_open(struct device_node *np, int channel);
int pmac_low_i2c_close(struct device_node *np);
int pmac_low_i2c_setmode(struct device_node *np, int mode);
int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len);
extern int pmac_i2c_open(struct pmac_i2c_bus *bus, int polled);
extern void pmac_i2c_close(struct pmac_i2c_bus *bus);
extern int pmac_i2c_setmode(struct pmac_i2c_bus *bus, int mode);
extern int pmac_i2c_xfer(struct pmac_i2c_bus *bus, u8 addrdir, int subsize,
u32 subaddr, u8 *data, int len);
/* Suspend/resume code called by via-pmu directly for now */
extern void pmac_pfunc_i2c_suspend(void);
extern void pmac_pfunc_i2c_resume(void);
#endif /* __KERNEL__ */
#endif /* __PMAC_LOW_I2C_H__ */

253
include/asm-powerpc/pmac_pfunc.h Normal file
View File

@@ -0,0 +1,253 @@
#ifndef __PMAC_PFUNC_H__
#define __PMAC_PFUNC_H__
#include <linux/types.h>
#include <linux/list.h>
/* Flags in command lists */
#define PMF_FLAGS_ON_INIT 0x80000000u
#define PMF_FLGAS_ON_TERM 0x40000000u
#define PMF_FLAGS_ON_SLEEP 0x20000000u
#define PMF_FLAGS_ON_WAKE 0x10000000u
#define PMF_FLAGS_ON_DEMAND 0x08000000u
#define PMF_FLAGS_INT_GEN 0x04000000u
#define PMF_FLAGS_HIGH_SPEED 0x02000000u
#define PMF_FLAGS_LOW_SPEED 0x01000000u
#define PMF_FLAGS_SIDE_EFFECTS 0x00800000u
/*
* Arguments to a platform function call.
*
* NOTE: By convention, pointer arguments point to an u32
*/
struct pmf_args {
union {
u32 v;
u32 *p;
} u[4];
unsigned int count;
};
/*
* A driver capable of interpreting commands provides a handlers
* structure filled with whatever handlers are implemented by this
* driver. Non implemented handlers are left NULL.
*
* PMF_STD_ARGS are the same arguments that are passed to the parser
* and that gets passed back to the various handlers.
*
* Interpreting a given function always start with a begin() call which
* returns an instance data to be passed around subsequent calls, and
* ends with an end() call. This allows the low level driver to implement
* locking policy or per-function instance data.
*
* For interrupt capable functions, irq_enable() is called when a client
* registers, and irq_disable() is called when the last client unregisters
* Note that irq_enable & irq_disable are called within a semaphore held
* by the core, thus you should not try to register yourself to some other
* pmf interrupt during those calls.
*/
#define PMF_STD_ARGS struct pmf_function *func, void *instdata, \
struct pmf_args *args
struct pmf_function;
struct pmf_handlers {
void * (*begin)(struct pmf_function *func, struct pmf_args *args);
void (*end)(struct pmf_function *func, void *instdata);
int (*irq_enable)(struct pmf_function *func);
int (*irq_disable)(struct pmf_function *func);
int (*write_gpio)(PMF_STD_ARGS, u8 value, u8 mask);
int (*read_gpio)(PMF_STD_ARGS, u8 mask, int rshift, u8 xor);
int (*write_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
int (*read_reg32)(PMF_STD_ARGS, u32 offset);
int (*write_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
int (*read_reg16)(PMF_STD_ARGS, u32 offset);
int (*write_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
int (*read_reg8)(PMF_STD_ARGS, u32 offset);
int (*delay)(PMF_STD_ARGS, u32 duration);
int (*wait_reg32)(PMF_STD_ARGS, u32 offset, u32 value, u32 mask);
int (*wait_reg16)(PMF_STD_ARGS, u32 offset, u16 value, u16 mask);
int (*wait_reg8)(PMF_STD_ARGS, u32 offset, u8 value, u8 mask);
int (*read_i2c)(PMF_STD_ARGS, u32 len);
int (*write_i2c)(PMF_STD_ARGS, u32 len, const u8 *data);
int (*rmw_i2c)(PMF_STD_ARGS, u32 masklen, u32 valuelen, u32 totallen,
const u8 *maskdata, const u8 *valuedata);
int (*read_cfg)(PMF_STD_ARGS, u32 offset, u32 len);
int (*write_cfg)(PMF_STD_ARGS, u32 offset, u32 len, const u8 *data);
int (*rmw_cfg)(PMF_STD_ARGS, u32 offset, u32 masklen, u32 valuelen,
u32 totallen, const u8 *maskdata, const u8 *valuedata);
int (*read_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len);
int (*write_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 len, const u8 *data);
int (*set_i2c_mode)(PMF_STD_ARGS, int mode);
int (*rmw_i2c_sub)(PMF_STD_ARGS, u8 subaddr, u32 masklen, u32 valuelen,
u32 totallen, const u8 *maskdata,
const u8 *valuedata);
int (*read_reg32_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
u32 xor);
int (*read_reg16_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
u32 xor);
int (*read_reg8_msrx)(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift,
u32 xor);
int (*write_reg32_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
int (*write_reg16_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
int (*write_reg8_slm)(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask);
int (*mask_and_compare)(PMF_STD_ARGS, u32 len, const u8 *maskdata,
const u8 *valuedata);
struct module *owner;
};
/*
* Drivers who expose platform functions register at init time, this
* causes the platform functions for that device node to be parsed in
* advance and associated with the device. The data structures are
* partially public so a driver can walk the list of platform functions
* and eventually inspect the flags
*/
struct pmf_device;
struct pmf_function {
/* All functions for a given driver are linked */
struct list_head link;
/* Function node & driver data */
struct device_node *node;
void *driver_data;
/* For internal use by core */
struct pmf_device *dev;
/* The name is the "xxx" in "platform-do-xxx", this is how
* platform functions are identified by this code. Some functions
* only operate for a given target, in which case the phandle is
* here (or 0 if the filter doesn't apply)
*/
const char *name;
u32 phandle;
/* The flags for that function. You can have several functions
* with the same name and different flag
*/
u32 flags;
/* The actual tokenized function blob */
const void *data;
unsigned int length;
/* Interrupt clients */
struct list_head irq_clients;
/* Refcounting */
struct kref ref;
};
/*
* For platform functions that are interrupts, one can register
* irq_client structures. You canNOT use the same structure twice
* as it contains a link member. Also, the callback is called with
* a spinlock held, you must not call back into any of the pmf_* functions
* from within that callback
*/
struct pmf_irq_client {
void (*handler)(void *data);
void *data;
struct module *owner;
struct list_head link;
};
/*
* Register/Unregister a function-capable driver and its handlers
*/
extern int pmf_register_driver(struct device_node *np,
struct pmf_handlers *handlers,
void *driverdata);
extern void pmf_unregister_driver(struct device_node *np);
/*
* Register/Unregister interrupt clients
*/
extern int pmf_register_irq_client(struct device_node *np,
const char *name,
struct pmf_irq_client *client);
extern void pmf_unregister_irq_client(struct device_node *np,
const char *name,
struct pmf_irq_client *client);
/*
* Called by the handlers when an irq happens
*/
extern void pmf_do_irq(struct pmf_function *func);
/*
* Low level call to platform functions.
*
* The phandle can filter on the target object for functions that have
* multiple targets, the flags allow you to restrict the call to a given
* combination of flags.
*
* The args array contains as many arguments as is required by the function,
* this is dependent on the function you are calling, unfortunately Apple
* mecanism provides no way to encode that so you have to get it right at
* the call site. Some functions require no args, in which case, you can
* pass NULL.
*
* You can also pass NULL to the name. This will match any function that has
* the appropriate combination of flags & phandle or you can pass 0 to the
* phandle to match any
*/
extern int pmf_do_functions(struct device_node *np, const char *name,
u32 phandle, u32 flags, struct pmf_args *args);
/*
* High level call to a platform function.
*
* This one looks for the platform-xxx first so you should call it to the
* actual target if any. It will fallback to platform-do-xxx if it can't
* find one. It will also exclusively target functions that have
* the "OnDemand" flag.
*/
extern int pmf_call_function(struct device_node *target, const char *name,
struct pmf_args *args);
/*
* For low latency interrupt usage, you can lookup for on-demand functions
* using the functions below
*/
extern struct pmf_function *pmf_find_function(struct device_node *target,
const char *name);
extern struct pmf_function * pmf_get_function(struct pmf_function *func);
extern void pmf_put_function(struct pmf_function *func);
extern int pmf_call_one(struct pmf_function *func, struct pmf_args *args);
/* Suspend/resume code called by via-pmu directly for now */
extern void pmac_pfunc_base_suspend(void);
extern void pmac_pfunc_base_resume(void);
#endif /* __PMAC_PFUNC_H__ */

2
include/asm-powerpc/pmc.h
View File

@@ -18,6 +18,7 @@
*/
#ifndef _POWERPC_PMC_H
#define _POWERPC_PMC_H
#ifdef __KERNEL__
#include <asm/ptrace.h>
@@ -44,4 +45,5 @@ void dump_pmcs(void);
extern struct op_powerpc_model op_model_fsl_booke;
#endif
#endif /* __KERNEL__ */
#endif /* _POWERPC_PMC_H */

2
include/asm-powerpc/ppc-pci.h
View File

@@ -8,6 +8,7 @@
*/
#ifndef _ASM_POWERPC_PPC_PCI_H
#define _ASM_POWERPC_PPC_PCI_H
#ifdef __KERNEL__
#include <linux/pci.h>
#include <asm/pci-bridge.h>
@@ -93,4 +94,5 @@ void eeh_clear_slot (struct device_node *dn, int mode_flag);
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PPC_PCI_H */

3
include/asm-powerpc/ppc_asm.h
View File

@@ -94,6 +94,7 @@
#define RFDI .long 0x4c00004e /* rfdi instruction */
#define RFMCI .long 0x4c00004c /* rfmci instruction */
#ifdef __KERNEL__
#ifdef CONFIG_PPC64
#define XGLUE(a,b) a##b
@@ -325,6 +326,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
#define CLR_TOP32(r)
#endif
#endif /* __KERNEL__ */
/* The boring bits... */
/* Condition Register Bit Fields */

5
include/asm-powerpc/processor.h
View File

@@ -10,7 +10,6 @@
* 2 of the License, or (at your option) any later version.
*/
#include <linux/config.h>
#include <asm/reg.h>
#ifndef __ASSEMBLY__
@@ -50,6 +49,7 @@
#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
#ifdef __KERNEL__
#define platform_is_pseries() (_machine == PLATFORM_PSERIES || \
_machine == PLATFORM_PSERIES_LPAR)
#define platform_is_lpar() (!!(_machine & PLATFORM_LPAR))
@@ -68,7 +68,6 @@ extern int _chrp_type;
* vendor. Board revision is also made available. This will be moved
* elsewhere soon
*/
extern unsigned char ucSystemType;
extern unsigned char ucBoardRev;
extern unsigned char ucBoardRevMaj, ucBoardRevMin;
@@ -82,7 +81,7 @@ extern unsigned char ucBoardRevMaj, ucBoardRevMin;
#else
#define _machine 0
#endif /* CONFIG_PPC_MULTIPLATFORM */
#endif /* __KERNEL__ */
/*
* Default implementation of macro that returns current
* instruction pointer ("program counter").

71
include/asm-powerpc/prom.h
View File

@@ -65,49 +65,11 @@ struct boot_param_header
typedef u32 phandle;
typedef u32 ihandle;
struct address_range {
unsigned long space;
unsigned long address;
unsigned long size;
};
struct interrupt_info {
int line;
int sense; /* +ve/-ve logic, edge or level, etc. */
};
struct pci_address {
u32 a_hi;
u32 a_mid;
u32 a_lo;
};
struct isa_address {
u32 a_hi;
u32 a_lo;
};
struct isa_range {
struct isa_address isa_addr;
struct pci_address pci_addr;
unsigned int size;
};
struct reg_property {
unsigned long address;
unsigned long size;
};
struct reg_property32 {
unsigned int address;
unsigned int size;
};
struct reg_property64 {
u64 address;
u64 size;
};
struct property {
char *name;
int length;
@@ -120,8 +82,6 @@ struct device_node {
char *type;
phandle node;
phandle linux_phandle;
int n_addrs;
struct address_range *addrs;
int n_intrs;
struct interrupt_info *intrs;
char *full_name;
@@ -223,5 +183,36 @@ extern struct resource *request_OF_resource(struct device_node* node,
int index, const char* name_postfix);
extern int release_OF_resource(struct device_node* node, int index);
/*
* OF address retreival & translation
*/
/* Translate an OF address block into a CPU physical address
*/
#define OF_BAD_ADDR ((u64)-1)
extern u64 of_translate_address(struct device_node *np, u32 *addr);
/* Extract an address from a device, returns the region size and
* the address space flags too. The PCI version uses a BAR number
* instead of an absolute index
*/
extern u32 *of_get_address(struct device_node *dev, int index,
u64 *size, unsigned int *flags);
extern u32 *of_get_pci_address(struct device_node *dev, int bar_no,
u64 *size, unsigned int *flags);
/* Get an address as a resource. Note that if your address is
* a PIO address, the conversion will fail if the physical address
* can't be internally converted to an IO token with
* pci_address_to_pio(), that is because it's either called to early
* or it can't be matched to any host bridge IO space
*/
extern int of_address_to_resource(struct device_node *dev, int index,
struct resource *r);
extern int of_pci_address_to_resource(struct device_node *dev, int bar,
struct resource *r);
#endif /* __KERNEL__ */
#endif /* _POWERPC_PROM_H */

2
include/asm-powerpc/ptrace.h
View File

@@ -87,7 +87,7 @@ extern unsigned long profile_pc(struct pt_regs *regs);
#define force_successful_syscall_return() \
do { \
current_thread_info()->syscall_noerror = 1; \
set_thread_flag(TIF_NOERROR); \
} while(0)
/*

58
include/asm-powerpc/reg.h
View File

@@ -145,6 +145,10 @@
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_CTRLF 0x088
#define SPRN_CTRLT 0x098
#define CTRL_CT 0xc0000000 /* current thread */
#define CTRL_CT0 0x80000000 /* thread 0 */
#define CTRL_CT1 0x40000000 /* thread 1 */
#define CTRL_TE 0x00c00000 /* thread enable */
#define CTRL_RUNLATCH 0x1
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
#define DABR_TRANSLATION (1UL << 2)
@@ -257,11 +261,11 @@
#define SPRN_HID6 0x3F9 /* BE HID 6 */
#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
#define SPRN_TSCR 0x399 /* Thread switch control on BE */
#define SPRN_TTR 0x39A /* Thread switch timeout on BE */
#define TSCR_DEC_ENABLE 0x200000 /* Decrementer Interrupt */
#define TSCR_EE_ENABLE 0x100000 /* External Interrupt */
#define TSCR_EE_BOOST 0x080000 /* External Interrupt Boost */
#define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */
#define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
#define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
#define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */
#define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */
#define SPRN_TSC 0x3FD /* Thread switch control on others */
#define SPRN_TST 0x3FC /* Thread switch timeout on others */
#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
@@ -375,6 +379,14 @@
#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */
#define SRR1_WAKERESET 0x00380000 /* System reset */
#define SRR1_WAKESYSERR 0x00300000 /* System error */
#define SRR1_WAKEEE 0x00200000 /* External interrupt */
#define SRR1_WAKEMT 0x00280000 /* mtctrl */
#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
#define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */
#ifndef SPRN_SVR
#define SPRN_SVR 0x11E /* System Version Register */
#endif
@@ -443,12 +455,35 @@
#define SPRN_SDAR 781
#else /* 32-bit */
#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
#define MMCR0_FC 0x80000000UL /* freeze counters */
#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
#define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/
#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
#define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
#define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
#define SPRN_MMCR1 956
#define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
#define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
#define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
#define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
#define SPRN_MMCR2 944
#define SPRN_PMC1 953 /* Performance Counter Register 1 */
#define SPRN_PMC2 954 /* Performance Counter Register 2 */
#define SPRN_PMC3 957 /* Performance Counter Register 3 */
#define SPRN_PMC4 958 /* Performance Counter Register 4 */
#define SPRN_PMC5 945 /* Performance Counter Register 5 */
#define SPRN_PMC6 946 /* Performance Counter Register 6 */
#define SPRN_SIAR 955 /* Sampled Instruction Address Register */
/* Bit definitions for MMCR0 and PMC1 / PMC2. */
#define MMCR0_PMC1_CYCLES (1 << 7)
@@ -458,7 +493,6 @@
#define MMCR0_PMC2_CYCLES 0x1
#define MMCR0_PMC2_ITLB 0x7
#define MMCR0_PMC2_LOADMISSTIME 0x5
#define MMCR0_PMXE (1 << 26)
#endif
/* Processor Version Register (PVR) field extraction */

2
include/asm-powerpc/rtas.h
View File

@@ -1,5 +1,6 @@
#ifndef _POWERPC_RTAS_H
#define _POWERPC_RTAS_H
#ifdef __KERNEL__
#include <linux/spinlock.h>
#include <asm/page.h>
@@ -229,4 +230,5 @@ extern unsigned long rtas_rmo_buf;
#define GLOBAL_INTERRUPT_QUEUE 9005
#endif /* __KERNEL__ */
#endif /* _POWERPC_RTAS_H */

4
include/asm-powerpc/seccomp.h
View File

@@ -1,6 +1,10 @@
#ifndef _ASM_POWERPC_SECCOMP_H
#define _ASM_POWERPC_SECCOMP_H
#ifdef __KERNEL__
#include <linux/thread_info.h>
#endif
#include <linux/unistd.h>
#define __NR_seccomp_read __NR_read

2
include/asm-powerpc/sections.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_SECTIONS_H
#define _ASM_POWERPC_SECTIONS_H
#ifdef __KERNEL__
#include <asm-generic/sections.h>
@@ -17,4 +18,5 @@ static inline int in_kernel_text(unsigned long addr)
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_SECTIONS_H */

2
include/asm-powerpc/serial.h
View File

@@ -15,4 +15,6 @@
/* Default baud base if not found in device-tree */
#define BASE_BAUD ( 1843200 / 16 )
extern void find_legacy_serial_ports(void);
#endif /* _PPC64_SERIAL_H */

7
include/asm-powerpc/signal.h
View File

@@ -2,10 +2,13 @@
#define _ASM_POWERPC_SIGNAL_H
#include <linux/types.h>
#include <linux/config.h>
#define _NSIG 64
#define _NSIG_BPW BITS_PER_LONG
#ifdef __powerpc64__
#define _NSIG_BPW 64
#else
#define _NSIG_BPW 32
#endif
#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
typedef unsigned long old_sigset_t; /* at least 32 bits */

34
include/asm-powerpc/smu.h
View File

@@ -4,9 +4,11 @@
/*
* Definitions for talking to the SMU chip in newer G5 PowerMacs
*/
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/list.h>
#endif
#include <linux/types.h>
/*
* Known SMU commands
@@ -356,6 +358,9 @@ extern unsigned long smu_cmdbuf_abs;
* Kenrel asynchronous i2c interface
*/
#define SMU_I2C_READ_MAX 0x1d
#define SMU_I2C_WRITE_MAX 0x15
/* SMU i2c header, exactly matches i2c header on wire */
struct smu_i2c_param
{
@@ -366,12 +371,9 @@ struct smu_i2c_param
u8 subaddr[3]; /* subaddress */
u8 caddr; /* combined address, filled by SMU driver */
u8 datalen; /* length of transfer */
u8 data[7]; /* data */
u8 data[SMU_I2C_READ_MAX]; /* data */
};
#define SMU_I2C_READ_MAX 0x0d
#define SMU_I2C_WRITE_MAX 0x05
struct smu_i2c_cmd
{
/* public */
@@ -385,7 +387,7 @@ struct smu_i2c_cmd
int read;
int stage;
int retries;
u8 pdata[0x10];
u8 pdata[32];
struct list_head link;
};
@@ -487,8 +489,8 @@ struct smu_sdbp_slotspow {
#define SMU_SDB_SENSORTREE_ID 0x25
struct smu_sdbp_sensortree {
u8 model_id;
u8 unknown[3];
__u8 model_id;
__u8 unknown[3];
};
/* This partition contains CPU thermal control PID informations. So far
@@ -498,13 +500,13 @@ struct smu_sdbp_sensortree {
#define SMU_SDB_CPUPIDDATA_ID 0x17
struct smu_sdbp_cpupiddata {
u8 unknown1;
u8 target_temp_delta;
u8 unknown2;
u8 history_len;
s16 power_adj;
u16 max_power;
s32 gp,gr,gd;
__u8 unknown1;
__u8 target_temp_delta;
__u8 unknown2;
__u8 history_len;
__s16 power_adj;
__u16 max_power;
__s32 gp,gr,gd;
};
@@ -517,7 +519,7 @@ struct smu_sdbp_cpupiddata {
* if not found. The data format is described below
*/
extern struct smu_sdbp_header *smu_get_sdb_partition(int id,
unsigned int *size);
unsigned int *size);
#endif /* __KERNEL__ */

10
include/asm-powerpc/sparsemem.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_SPARSEMEM_H
#define _ASM_POWERPC_SPARSEMEM_H 1
#ifdef __KERNEL__
#ifdef CONFIG_SPARSEMEM
/*
@@ -13,8 +14,17 @@
#ifdef CONFIG_MEMORY_HOTPLUG
extern void create_section_mapping(unsigned long start, unsigned long end);
#ifdef CONFIG_NUMA
extern int hot_add_scn_to_nid(unsigned long scn_addr);
#else
static inline int hot_add_scn_to_nid(unsigned long scn_addr)
{
return 0;
}
#endif /* CONFIG_NUMA */
#endif /* CONFIG_MEMORY_HOTPLUG */
#endif /* CONFIG_SPARSEMEM */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_SPARSEMEM_H */

2
include/asm-powerpc/spinlock.h
View File

@@ -1,5 +1,6 @@
#ifndef __ASM_SPINLOCK_H
#define __ASM_SPINLOCK_H
#ifdef __KERNEL__
/*
* Simple spin lock operations.
@@ -266,4 +267,5 @@ static __inline__ void __raw_write_unlock(raw_rwlock_t *rw)
rw->lock = 0;
}
#endif /* __KERNEL__ */
#endif /* __ASM_SPINLOCK_H */

600
include/asm-powerpc/spu.h Normal file
View File

@@ -0,0 +1,600 @@
/*
* SPU core / file system interface and HW structures
*
* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
*
* Author: Arnd Bergmann <arndb@de.ibm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _SPU_H
#define _SPU_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/kref.h>
#include <linux/workqueue.h>
#define LS_SIZE (256 * 1024)
#define LS_ADDR_MASK (LS_SIZE - 1)
#define MFC_PUT_CMD 0x20
#define MFC_PUTS_CMD 0x28
#define MFC_PUTR_CMD 0x30
#define MFC_PUTF_CMD 0x22
#define MFC_PUTB_CMD 0x21
#define MFC_PUTFS_CMD 0x2A
#define MFC_PUTBS_CMD 0x29
#define MFC_PUTRF_CMD 0x32
#define MFC_PUTRB_CMD 0x31
#define MFC_PUTL_CMD 0x24
#define MFC_PUTRL_CMD 0x34
#define MFC_PUTLF_CMD 0x26
#define MFC_PUTLB_CMD 0x25
#define MFC_PUTRLF_CMD 0x36
#define MFC_PUTRLB_CMD 0x35
#define MFC_GET_CMD 0x40
#define MFC_GETS_CMD 0x48
#define MFC_GETF_CMD 0x42
#define MFC_GETB_CMD 0x41
#define MFC_GETFS_CMD 0x4A
#define MFC_GETBS_CMD 0x49
#define MFC_GETL_CMD 0x44
#define MFC_GETLF_CMD 0x46
#define MFC_GETLB_CMD 0x45
#define MFC_SDCRT_CMD 0x80
#define MFC_SDCRTST_CMD 0x81
#define MFC_SDCRZ_CMD 0x89
#define MFC_SDCRS_CMD 0x8D
#define MFC_SDCRF_CMD 0x8F
#define MFC_GETLLAR_CMD 0xD0
#define MFC_PUTLLC_CMD 0xB4
#define MFC_PUTLLUC_CMD 0xB0
#define MFC_PUTQLLUC_CMD 0xB8
#define MFC_SNDSIG_CMD 0xA0
#define MFC_SNDSIGB_CMD 0xA1
#define MFC_SNDSIGF_CMD 0xA2
#define MFC_BARRIER_CMD 0xC0
#define MFC_EIEIO_CMD 0xC8
#define MFC_SYNC_CMD 0xCC
#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
/* Events for Channels 0-2 */
#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
#define MFC_DECREMENTER_EVENT 0x00000020
#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
#define MFC_SIGNAL_2_EVENT 0x00000100
#define MFC_SIGNAL_1_EVENT 0x00000200
#define MFC_LLR_LOST_EVENT 0x00000400
#define MFC_PRIV_ATTN_EVENT 0x00000800
#define MFC_MULTI_SRC_EVENT 0x00001000
/* Flags indicating progress during context switch. */
#define SPU_CONTEXT_SWITCH_PENDING 0UL
#define SPU_CONTEXT_SWITCH_ACTIVE 1UL
struct spu_context;
struct spu_runqueue;
struct spu {
char *name;
unsigned long local_store_phys;
u8 *local_store;
struct spu_problem __iomem *problem;
struct spu_priv1 __iomem *priv1;
struct spu_priv2 __iomem *priv2;
struct list_head list;
struct list_head sched_list;
int number;
u32 isrc;
u32 node;
u64 flags;
u64 dar;
u64 dsisr;
struct kref kref;
size_t ls_size;
unsigned int slb_replace;
struct mm_struct *mm;
struct spu_context *ctx;
struct spu_runqueue *rq;
unsigned long long timestamp;
pid_t pid;
int prio;
int class_0_pending;
spinlock_t register_lock;
u32 stop_code;
void (* wbox_callback)(struct spu *spu);
void (* ibox_callback)(struct spu *spu);
void (* stop_callback)(struct spu *spu);
char irq_c0[8];
char irq_c1[8];
char irq_c2[8];
};
struct spu *spu_alloc(void);
void spu_free(struct spu *spu);
int spu_irq_class_0_bottom(struct spu *spu);
int spu_irq_class_1_bottom(struct spu *spu);
void spu_irq_setaffinity(struct spu *spu, int cpu);
extern struct spufs_calls {
asmlinkage long (*create_thread)(const char __user *name,
unsigned int flags, mode_t mode);
asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
__u32 __user *ustatus);
struct module *owner;
} spufs_calls;
#ifdef CONFIG_SPU_FS_MODULE
int register_spu_syscalls(struct spufs_calls *calls);
void unregister_spu_syscalls(struct spufs_calls *calls);
#else
static inline int register_spu_syscalls(struct spufs_calls *calls)
{
return 0;
}
static inline void unregister_spu_syscalls(struct spufs_calls *calls)
{
}
#endif /* MODULE */
/* access to priv1 registers */
void spu_int_mask_and(struct spu *spu, int class, u64 mask);
void spu_int_mask_or(struct spu *spu, int class, u64 mask);
void spu_int_mask_set(struct spu *spu, int class, u64 mask);
u64 spu_int_mask_get(struct spu *spu, int class);
void spu_int_stat_clear(struct spu *spu, int class, u64 stat);
u64 spu_int_stat_get(struct spu *spu, int class);
void spu_int_route_set(struct spu *spu, u64 route);
u64 spu_mfc_dar_get(struct spu *spu);
u64 spu_mfc_dsisr_get(struct spu *spu);
void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr);
void spu_mfc_sdr_set(struct spu *spu, u64 sdr);
void spu_mfc_sr1_set(struct spu *spu, u64 sr1);
u64 spu_mfc_sr1_get(struct spu *spu);
void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id);
u64 spu_mfc_tclass_id_get(struct spu *spu);
void spu_tlb_invalidate(struct spu *spu);
void spu_resource_allocation_groupID_set(struct spu *spu, u64 id);
u64 spu_resource_allocation_groupID_get(struct spu *spu);
void spu_resource_allocation_enable_set(struct spu *spu, u64 enable);
u64 spu_resource_allocation_enable_get(struct spu *spu);
/*
* This defines the Local Store, Problem Area and Privlege Area of an SPU.
*/
union mfc_tag_size_class_cmd {
struct {
u16 mfc_size;
u16 mfc_tag;
u8 pad;
u8 mfc_rclassid;
u16 mfc_cmd;
} u;
struct {
u32 mfc_size_tag32;
u32 mfc_class_cmd32;
} by32;
u64 all64;
};
struct mfc_cq_sr {
u64 mfc_cq_data0_RW;
u64 mfc_cq_data1_RW;
u64 mfc_cq_data2_RW;
u64 mfc_cq_data3_RW;
};
struct spu_problem {
#define MS_SYNC_PENDING 1L
u64 spc_mssync_RW; /* 0x0000 */
u8 pad_0x0008_0x3000[0x3000 - 0x0008];
/* DMA Area */
u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
u32 mfc_lsa_W; /* 0x3004 */
u64 mfc_ea_W; /* 0x3008 */
union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
u32 dma_qstatus_R; /* 0x3104 */
u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
u32 dma_querytype_RW; /* 0x3204 */
u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
u32 dma_querymask_RW; /* 0x321c */
u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
u32 dma_tagstatus_R; /* 0x322c */
#define DMA_TAGSTATUS_INTR_ANY 1u
#define DMA_TAGSTATUS_INTR_ALL 2u
u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
/* SPU Control Area */
u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
u32 pu_mb_R; /* 0x4004 */
u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
u32 spu_mb_W; /* 0x400c */
u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
u32 mb_stat_R; /* 0x4014 */
u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
u32 spu_runcntl_RW; /* 0x401c */
#define SPU_RUNCNTL_STOP 0L
#define SPU_RUNCNTL_RUNNABLE 1L
u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
u32 spu_status_R; /* 0x4024 */
#define SPU_STOP_STATUS_SHIFT 16
#define SPU_STATUS_STOPPED 0x0
#define SPU_STATUS_RUNNING 0x1
#define SPU_STATUS_STOPPED_BY_STOP 0x2
#define SPU_STATUS_STOPPED_BY_HALT 0x4
#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
#define SPU_STATUS_SINGLE_STEP 0x10
#define SPU_STATUS_INVALID_INSTR 0x20
#define SPU_STATUS_INVALID_CH 0x40
#define SPU_STATUS_ISOLATED_STATE 0x80
#define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
#define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
u32 spu_spe_R; /* 0x402c */
u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
u32 spu_npc_RW; /* 0x4034 */
u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
/* Signal Notification Area */
u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
u32 signal_notify1; /* 0x1400c */
u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
u32 signal_notify2; /* 0x1c00c */
} __attribute__ ((aligned(0x20000)));
/* SPU Privilege 2 State Area */
struct spu_priv2 {
/* MFC Registers */
u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
/* SLB Management Registers */
u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
u64 slb_index_W; /* 0x1108 */
#define SLB_INDEX_MASK 0x7L
u64 slb_esid_RW; /* 0x1110 */
u64 slb_vsid_RW; /* 0x1118 */
#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
#define SLB_VSID_4K_PAGE (0x0 << 8)
#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
#define SLB_VSID_CLASS_MASK (0x1ull << 7)
#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
u64 slb_invalidate_entry_W; /* 0x1120 */
u64 slb_invalidate_all_W; /* 0x1128 */
u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
/* Context Save / Restore Area */
struct mfc_cq_sr spuq[16]; /* 0x2000 */
struct mfc_cq_sr puq[8]; /* 0x2200 */
u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
/* MFC Control */
u64 mfc_control_RW; /* 0x3000 */
#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
/* Interrupt Mailbox */
u64 puint_mb_R; /* 0x4000 */
u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
/* SPU Control */
u64 spu_privcntl_RW; /* 0x4040 */
#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
u64 spu_lslr_RW; /* 0x4058 */
u64 spu_chnlcntptr_RW; /* 0x4060 */
u64 spu_chnlcnt_RW; /* 0x4068 */
u64 spu_chnldata_RW; /* 0x4070 */
u64 spu_cfg_RW; /* 0x4078 */
u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
/* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
u64 spu_tag_status_query_RW; /* 0x5008 */
#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
u64 spu_cmd_buf1_RW; /* 0x5010 */
#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
u64 spu_cmd_buf2_RW; /* 0x5018 */
#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
u64 spu_atomic_status_RW; /* 0x5020 */
} __attribute__ ((aligned(0x20000)));
/* SPU Privilege 1 State Area */
struct spu_priv1 {
/* Control and Configuration Area */
u64 mfc_sr1_RW; /* 0x000 */
#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
#define MFC_STATE1_RELOCATE_MASK 0x10ull
#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
u64 mfc_lpid_RW; /* 0x008 */
u64 spu_idr_RW; /* 0x010 */
u64 mfc_vr_RO; /* 0x018 */
#define MFC_VERSION_BITS (0xffff << 16)
#define MFC_REVISION_BITS (0xffff)
#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
u64 spu_vr_RO; /* 0x020 */
#define SPU_VERSION_BITS (0xffff << 16)
#define SPU_REVISION_BITS (0xffff)
#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
/* Interrupt Area */
u64 int_mask_RW[3]; /* 0x100 */
#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
u8 pad_0x118_0x140[0x28]; /* 0x118 */
u64 int_stat_RW[3]; /* 0x140 */
u8 pad_0x158_0x180[0x28]; /* 0x158 */
u64 int_route_RW; /* 0x180 */
/* Interrupt Routing */
u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
/* Atomic Unit Control Area */
u64 mfc_atomic_flush_RW; /* 0x200 */
#define mfc_atomic_flush_enable 0x1L
u8 pad_0x208_0x280[0x78]; /* 0x208 */
u64 resource_allocation_groupID_RW; /* 0x280 */
u64 resource_allocation_enable_RW; /* 0x288 */
u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
/* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
u64 smf_sbi_signal_sel; /* 0x3c8 */
#define smf_sbi_mask_lsb 56
#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
#define smf_sbi_mask (0x301LL << smf_sbi_shift)
#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
u64 smf_ato_signal_sel; /* 0x3d0 */
#define smf_ato_mask_lsb 35
#define smf_ato_shift (63 - smf_ato_mask_lsb)
#define smf_ato_mask (0x3LL << smf_ato_shift)
#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
/* TLB Management Registers */
u64 mfc_sdr_RW; /* 0x400 */
u8 pad_0x408_0x500[0xf8]; /* 0x408 */
u64 tlb_index_hint_RO; /* 0x500 */
u64 tlb_index_W; /* 0x508 */
u64 tlb_vpn_RW; /* 0x510 */
u64 tlb_rpn_RW; /* 0x518 */
u8 pad_0x520_0x540[0x20]; /* 0x520 */
u64 tlb_invalidate_entry_W; /* 0x540 */
u64 tlb_invalidate_all_W; /* 0x548 */
u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
/* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
u64 smm_hid; /* 0x580 */
#define PAGE_SIZE_MASK 0xf000000000000000ull
#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
/* MFC Status/Control Area */
u64 mfc_accr_RW; /* 0x600 */
#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
u8 pad_0x608_0x610[0x8]; /* 0x608 */
u64 mfc_dsisr_RW; /* 0x610 */
#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
#define MFC_DSISR_ACCESS_DENIED (1 << 27)
#define MFC_DSISR_ATOMIC (1 << 26)
#define MFC_DSISR_ACCESS_PUT (1 << 25)
#define MFC_DSISR_ADDR_MATCH (1 << 22)
#define MFC_DSISR_LS (1 << 17)
#define MFC_DSISR_L (1 << 16)
#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
u8 pad_0x618_0x620[0x8]; /* 0x618 */
u64 mfc_dar_RW; /* 0x620 */
u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
/* Replacement Management Table (RMT) Area */
u64 rmt_index_RW; /* 0x700 */
u8 pad_0x708_0x710[0x8]; /* 0x708 */
u64 rmt_data1_RW; /* 0x710 */
u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
/* Control/Configuration Registers */
u64 mfc_dsir_R; /* 0x800 */
#define MFC_DSIR_Q (1 << 31)
#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
u64 mfc_lsacr_RW; /* 0x808 */
#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
u64 mfc_lscrr_R; /* 0x810 */
#define MFC_LSCRR_Q (1 << 31)
#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
#define MFC_LSCRR_QI_SHIFT 32
#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
u8 pad_0x818_0x820[0x8]; /* 0x818 */
u64 mfc_tclass_id_RW; /* 0x820 */
#define MFC_TCLASS_ID_ENABLE (1L << 0L)
#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
#define MFC_TCLASS_QUOTA_2_SHIFT 8L
#define MFC_TCLASS_QUOTA_1_SHIFT 16L
#define MFC_TCLASS_QUOTA_0_SHIFT 24L
#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
/* Real Mode Support Registers */
u64 mfc_rm_boundary; /* 0x900 */
u8 pad_0x908_0x938[0x30]; /* 0x908 */
u64 smf_dma_signal_sel; /* 0x938 */
#define mfc_dma1_mask_lsb 41
#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
#define mfc_dma2_mask_lsb 43
#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
u64 smm_signal_sel; /* 0xa38 */
#define smm_sig_mask_lsb 12
#define smm_sig_shift (63 - smm_sig_mask_lsb)
#define smm_sig_mask (0x3LL << smm_sig_shift)
#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
/* DMA Command Error Area */
u64 mfc_cer_R; /* 0xc00 */
#define MFC_CER_Q (1 << 31)
#define MFC_CER_SPU_QUEUE MFC_CER_Q
u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
/* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
/* DMA Command Error Area */
u64 spu_ecc_cntl_RW; /* 0x1000 */
#define SPU_ECC_CNTL_E (1ull << 0ull)
#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
#define SPU_ECC_CNTL_S (1ull << 1ull)
#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
#define SPU_ECC_CNTL_B (1ull << 2ull)
#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
#define SPU_ECC_CNTL_I_SHIFT 3ull
#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
#define SPU_ECC_CNTL_D (1ull << 5ull)
#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
u64 spu_ecc_stat_RW; /* 0x1008 */
#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
#define SPU_ECC_DATA_ERROR (1ull << 5ul)
#define SPU_ECC_DMA_ERROR (1ull << 6ul)
#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
u64 spu_ecc_addr_RW; /* 0x1010 */
u64 spu_err_mask_RW; /* 0x1018 */
#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
/* SPU Debug-Trace Bus (DTB) Selection Registers */
u64 spu_trig0_sel; /* 0x1028 */
u64 spu_trig1_sel; /* 0x1030 */
u64 spu_trig2_sel; /* 0x1038 */
u64 spu_trig3_sel; /* 0x1040 */
u64 spu_trace_sel; /* 0x1048 */
#define spu_trace_sel_mask 0x1f1fLL
#define spu_trace_sel_bus0_bits 0x1000LL
#define spu_trace_sel_bus2_bits 0x0010LL
u64 spu_event0_sel; /* 0x1050 */
u64 spu_event1_sel; /* 0x1058 */
u64 spu_event2_sel; /* 0x1060 */
u64 spu_event3_sel; /* 0x1068 */
u64 spu_trace_cntl; /* 0x1070 */
} __attribute__ ((aligned(0x2000)));
#endif /* __KERNEL__ */
#endif

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include/asm-powerpc/spu_csa.h Normal file
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/*
* spu_csa.h: Definitions for SPU context save area (CSA).
*
* (C) Copyright IBM 2005
*
* Author: Mark Nutter <mnutter@us.ibm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _SPU_CSA_H_
#define _SPU_CSA_H_
#ifdef __KERNEL__
/*
* Total number of 128-bit registers.
*/
#define NR_SPU_GPRS 128
#define NR_SPU_SPRS 9
#define NR_SPU_REGS_PAD 7
#define NR_SPU_SPILL_REGS 144 /* GPRS + SPRS + PAD */
#define SIZEOF_SPU_SPILL_REGS NR_SPU_SPILL_REGS * 16
#define SPU_SAVE_COMPLETE 0x3FFB
#define SPU_RESTORE_COMPLETE 0x3FFC
/*
* Definitions for various 'stopped' status conditions,
* to be recreated during context restore.
*/
#define SPU_STOPPED_STATUS_P 1
#define SPU_STOPPED_STATUS_I 2
#define SPU_STOPPED_STATUS_H 3
#define SPU_STOPPED_STATUS_S 4
#define SPU_STOPPED_STATUS_S_I 5
#define SPU_STOPPED_STATUS_S_P 6
#define SPU_STOPPED_STATUS_P_H 7
#define SPU_STOPPED_STATUS_P_I 8
#define SPU_STOPPED_STATUS_R 9
#ifndef __ASSEMBLY__
/**
* spu_reg128 - generic 128-bit register definition.
*/
struct spu_reg128 {
u32 slot[4];
};
/**
* struct spu_lscsa - Local Store Context Save Area.
* @gprs: Array of saved registers.
* @fpcr: Saved floating point status control register.
* @decr: Saved decrementer value.
* @decr_status: Indicates decrementer run status.
* @ppu_mb: Saved PPU mailbox data.
* @ppuint_mb: Saved PPU interrupting mailbox data.
* @tag_mask: Saved tag group mask.
* @event_mask: Saved event mask.
* @srr0: Saved SRR0.
* @stopped_status: Conditions to be recreated by restore.
* @ls: Saved contents of Local Storage Area.
*
* The LSCSA represents state that is primarily saved and
* restored by SPU-side code.
*/
struct spu_lscsa {
struct spu_reg128 gprs[128];
struct spu_reg128 fpcr;
struct spu_reg128 decr;
struct spu_reg128 decr_status;
struct spu_reg128 ppu_mb;
struct spu_reg128 ppuint_mb;
struct spu_reg128 tag_mask;
struct spu_reg128 event_mask;
struct spu_reg128 srr0;
struct spu_reg128 stopped_status;
struct spu_reg128 pad[119]; /* 'ls' must be page-aligned. */
unsigned char ls[LS_SIZE];
};
/*
* struct spu_problem_collapsed - condensed problem state area, w/o pads.
*/
struct spu_problem_collapsed {
u64 spc_mssync_RW;
u32 mfc_lsa_W;
u32 unused_pad0;
u64 mfc_ea_W;
union mfc_tag_size_class_cmd mfc_union_W;
u32 dma_qstatus_R;
u32 dma_querytype_RW;
u32 dma_querymask_RW;
u32 dma_tagstatus_R;
u32 pu_mb_R;
u32 spu_mb_W;
u32 mb_stat_R;
u32 spu_runcntl_RW;
u32 spu_status_R;
u32 spu_spc_R;
u32 spu_npc_RW;
u32 signal_notify1;
u32 signal_notify2;
u32 unused_pad1;
};
/*
* struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads.
*/
struct spu_priv1_collapsed {
u64 mfc_sr1_RW;
u64 mfc_lpid_RW;
u64 spu_idr_RW;
u64 mfc_vr_RO;
u64 spu_vr_RO;
u64 int_mask_class0_RW;
u64 int_mask_class1_RW;
u64 int_mask_class2_RW;
u64 int_stat_class0_RW;
u64 int_stat_class1_RW;
u64 int_stat_class2_RW;
u64 int_route_RW;
u64 mfc_atomic_flush_RW;
u64 resource_allocation_groupID_RW;
u64 resource_allocation_enable_RW;
u64 mfc_fir_R;
u64 mfc_fir_status_or_W;
u64 mfc_fir_status_and_W;
u64 mfc_fir_mask_R;
u64 mfc_fir_mask_or_W;
u64 mfc_fir_mask_and_W;
u64 mfc_fir_chkstp_enable_RW;
u64 smf_sbi_signal_sel;
u64 smf_ato_signal_sel;
u64 mfc_sdr_RW;
u64 tlb_index_hint_RO;
u64 tlb_index_W;
u64 tlb_vpn_RW;
u64 tlb_rpn_RW;
u64 tlb_invalidate_entry_W;
u64 tlb_invalidate_all_W;
u64 smm_hid;
u64 mfc_accr_RW;
u64 mfc_dsisr_RW;
u64 mfc_dar_RW;
u64 rmt_index_RW;
u64 rmt_data1_RW;
u64 mfc_dsir_R;
u64 mfc_lsacr_RW;
u64 mfc_lscrr_R;
u64 mfc_tclass_id_RW;
u64 mfc_rm_boundary;
u64 smf_dma_signal_sel;
u64 smm_signal_sel;
u64 mfc_cer_R;
u64 pu_ecc_cntl_RW;
u64 pu_ecc_stat_RW;
u64 spu_ecc_addr_RW;
u64 spu_err_mask_RW;
u64 spu_trig0_sel;
u64 spu_trig1_sel;
u64 spu_trig2_sel;
u64 spu_trig3_sel;
u64 spu_trace_sel;
u64 spu_event0_sel;
u64 spu_event1_sel;
u64 spu_event2_sel;
u64 spu_event3_sel;
u64 spu_trace_cntl;
};
/*
* struct spu_priv2_collapsed - condensed priviliged 2 area, w/o pads.
*/
struct spu_priv2_collapsed {
u64 slb_index_W;
u64 slb_esid_RW;
u64 slb_vsid_RW;
u64 slb_invalidate_entry_W;
u64 slb_invalidate_all_W;
struct mfc_cq_sr spuq[16];
struct mfc_cq_sr puq[8];
u64 mfc_control_RW;
u64 puint_mb_R;
u64 spu_privcntl_RW;
u64 spu_lslr_RW;
u64 spu_chnlcntptr_RW;
u64 spu_chnlcnt_RW;
u64 spu_chnldata_RW;
u64 spu_cfg_RW;
u64 spu_tag_status_query_RW;
u64 spu_cmd_buf1_RW;
u64 spu_cmd_buf2_RW;
u64 spu_atomic_status_RW;
};
/**
* struct spu_state
* @lscsa: Local Store Context Save Area.
* @prob: Collapsed Problem State Area, w/o pads.
* @priv1: Collapsed Privileged 1 Area, w/o pads.
* @priv2: Collapsed Privileged 2 Area, w/o pads.
* @spu_chnlcnt_RW: Array of saved channel counts.
* @spu_chnldata_RW: Array of saved channel data.
* @suspend_time: Time stamp when decrementer disabled.
* @slb_esid_RW: Array of saved SLB esid entries.
* @slb_vsid_RW: Array of saved SLB vsid entries.
*
* Structure representing the whole of the SPU
* context save area (CSA). This struct contains
* all of the state necessary to suspend and then
* later optionally resume execution of an SPU
* context.
*
* The @lscsa region is by far the largest, and is
* allocated separately so that it may either be
* pinned or mapped to/from application memory, as
* appropriate for the OS environment.
*/
struct spu_state {
struct spu_lscsa *lscsa;
struct spu_problem_collapsed prob;
struct spu_priv1_collapsed priv1;
struct spu_priv2_collapsed priv2;
u64 spu_chnlcnt_RW[32];
u64 spu_chnldata_RW[32];
u32 spu_mailbox_data[4];
u32 pu_mailbox_data[1];
unsigned long suspend_time;
u64 slb_esid_RW[8];
u64 slb_vsid_RW[8];
spinlock_t register_lock;
};
extern void spu_init_csa(struct spu_state *csa);
extern void spu_fini_csa(struct spu_state *csa);
extern int spu_save(struct spu_state *prev, struct spu *spu);
extern int spu_restore(struct spu_state *new, struct spu *spu);
extern int spu_switch(struct spu_state *prev, struct spu_state *new,
struct spu *spu);
#endif /* __KERNEL__ */
#endif /* !__ASSEMBLY__ */
#endif /* _SPU_CSA_H_ */

4
include/asm-powerpc/synch.h
View File

@@ -1,7 +1,6 @@
#ifndef _ASM_POWERPC_SYNCH_H
#define _ASM_POWERPC_SYNCH_H
#include <linux/config.h>
#ifdef __KERNEL__
#ifdef __powerpc64__
#define __SUBARCH_HAS_LWSYNC
@@ -47,5 +46,6 @@ static inline void isync(void)
#define isync_on_smp() __asm__ __volatile__("": : :"memory")
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_SYNCH_H */

3
include/asm-powerpc/system.h
View File

@@ -4,7 +4,6 @@
#ifndef _ASM_POWERPC_SYSTEM_H
#define _ASM_POWERPC_SYSTEM_H
#include <linux/config.h>
#include <linux/kernel.h>
#include <asm/hw_irq.h>
@@ -42,6 +41,7 @@
#define set_mb(var, value) do { var = value; mb(); } while (0)
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
#ifdef __KERNEL__
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
@@ -54,7 +54,6 @@
#define smp_read_barrier_depends() do { } while(0)
#endif /* CONFIG_SMP */
#ifdef __KERNEL__
struct task_struct;
struct pt_regs;

2
include/asm-powerpc/tce.h
View File

@@ -20,6 +20,7 @@
#ifndef _ASM_POWERPC_TCE_H
#define _ASM_POWERPC_TCE_H
#ifdef __KERNEL__
/*
* Tces come in two formats, one for the virtual bus and a different
@@ -61,4 +62,5 @@ union tce_entry {
};
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_TCE_H */

12
include/asm-powerpc/thread_info.h
View File

@@ -37,8 +37,7 @@ struct thread_info {
int preempt_count; /* 0 => preemptable,
<0 => BUG */
struct restart_block restart_block;
/* set by force_successful_syscall_return */
unsigned char syscall_noerror;
void *nvgprs_frame;
/* low level flags - has atomic operations done on it */
unsigned long flags ____cacheline_aligned_in_smp;
};
@@ -123,6 +122,9 @@ static inline struct thread_info *current_thread_info(void)
#define TIF_SINGLESTEP 9 /* singlestepping active */
#define TIF_MEMDIE 10
#define TIF_SECCOMP 11 /* secure computing */
#define TIF_RESTOREALL 12 /* Restore all regs (implies NOERROR) */
#define TIF_SAVE_NVGPRS 13 /* Save r14-r31 in signal frame */
#define TIF_NOERROR 14 /* Force successful syscall return */
/* as above, but as bit values */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -136,10 +138,14 @@ static inline struct thread_info *current_thread_info(void)
#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
#define _TIF_SECCOMP (1<<TIF_SECCOMP)
#define _TIF_RESTOREALL (1<<TIF_RESTOREALL)
#define _TIF_SAVE_NVGPRS (1<<TIF_SAVE_NVGPRS)
#define _TIF_NOERROR (1<<TIF_NOERROR)
#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
#define _TIF_USER_WORK_MASK (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | \
_TIF_NEED_RESCHED)
_TIF_NEED_RESCHED | _TIF_RESTOREALL)
#define _TIF_PERSYSCALL_MASK (_TIF_RESTOREALL|_TIF_NOERROR|_TIF_SAVE_NVGPRS)
#endif /* __KERNEL__ */

2
include/asm-powerpc/tlb.h
View File

@@ -11,6 +11,7 @@
*/
#ifndef _ASM_POWERPC_TLB_H
#define _ASM_POWERPC_TLB_H
#ifdef __KERNEL__
#include <linux/config.h>
#ifndef __powerpc64__
@@ -67,4 +68,5 @@ static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
}
#endif
#endif /* __KERNEL__ */
#endif /* __ASM_POWERPC_TLB_H */

6
include/asm-powerpc/topology.h
View File

@@ -1,5 +1,6 @@
#ifndef _ASM_POWERPC_TOPOLOGY_H
#define _ASM_POWERPC_TOPOLOGY_H
#ifdef __KERNEL__
#include <linux/config.h>
@@ -55,10 +56,15 @@ static inline int node_to_first_cpu(int node)
.nr_balance_failed = 0, \
}
extern void __init dump_numa_cpu_topology(void);
#else
static inline void dump_numa_cpu_topology(void) {}
#include <asm-generic/topology.h>
#endif /* CONFIG_NUMA */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_TOPOLOGY_H */

17
include/asm-powerpc/udbg.h
View File

@@ -9,12 +9,13 @@
#ifndef _ASM_POWERPC_UDBG_H
#define _ASM_POWERPC_UDBG_H
#ifdef __KERNEL__
#include <linux/compiler.h>
#include <linux/init.h>
extern void (*udbg_putc)(unsigned char c);
extern unsigned char (*udbg_getc)(void);
extern void (*udbg_putc)(char c);
extern int (*udbg_getc)(void);
extern int (*udbg_getc_poll)(void);
extern void udbg_puts(const char *s);
@@ -23,9 +24,17 @@ extern int udbg_read(char *buf, int buflen);
extern void register_early_udbg_console(void);
extern void udbg_printf(const char *fmt, ...);
extern void udbg_progress(char *s, unsigned short hex);
extern void udbg_init_uart(void __iomem *comport, unsigned int speed);
extern void udbg_init_uart(void __iomem *comport, unsigned int speed,
unsigned int clock);
extern unsigned int udbg_probe_uart_speed(void __iomem *comport,
unsigned int clock);
struct device_node;
extern void udbg_init_scc(struct device_node *np);
extern void udbg_scc_init(int force_scc);
extern int udbg_adb_init(int force_btext);
extern void udbg_adb_init_early(void);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_UDBG_H */

4
include/asm-powerpc/unistd.h
View File

@@ -296,8 +296,10 @@
#define __NR_inotify_init 275
#define __NR_inotify_add_watch 276
#define __NR_inotify_rm_watch 277
#define __NR_spu_run 278
#define __NR_spu_create 279
#define __NR_syscalls 278
#define __NR_syscalls 280
#ifdef __KERNEL__
#define __NR__exit __NR_exit

2
include/asm-powerpc/vdso_datapage.h
View File

@@ -1,5 +1,6 @@
#ifndef _VDSO_DATAPAGE_H
#define _VDSO_DATAPAGE_H
#ifdef __KERNEL__
/*
* Copyright (C) 2002 Peter Bergner <bergner@vnet.ibm.com>, IBM
@@ -105,4 +106,5 @@ extern struct vdso_data *vdso_data;
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _SYSTEMCFG_H */

2
include/asm-powerpc/vio.h
View File

@@ -13,6 +13,7 @@
#ifndef _ASM_POWERPC_VIO_H
#define _ASM_POWERPC_VIO_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/init.h>
@@ -103,4 +104,5 @@ static inline struct vio_dev *to_vio_dev(struct device *dev)
return container_of(dev, struct vio_dev, dev);
}
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_VIO_H */