powerpc/powernv: Add support for p5ioc2 PCI-X and PCIe
This adds support for PCI-X and PCIe on the p5ioc2 IO hub using OPAL. This includes allocating & setting up TCE tables and config space access routines. This also supports fallbacks via RTAS when OPAL is absent, using legacy TCE format pre-allocated via the device-tree (BML style) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
286
arch/powerpc/platforms/powernv/pci.c
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286
arch/powerpc/platforms/powernv/pci.c
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/*
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* Support PCI/PCIe on PowerNV platforms
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*
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* Currently supports only P5IOC2
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*
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* Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/ppc-pci.h>
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#include <asm/opal.h>
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#include <asm/iommu.h>
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#include <asm/tce.h>
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#include <asm/abs_addr.h>
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#include "powernv.h"
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#include "pci.h"
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#define cfg_dbg(fmt...) do { } while(0)
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//#define cfg_dbg(fmt...) printk(fmt)
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static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
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u32 bdfn)
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{
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s64 rc;
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u8 fstate;
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u16 pcierr;
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u32 pe_no;
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/* Get PE# if we support IODA */
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pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;
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/* Read freeze status */
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rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
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NULL);
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if (rc) {
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pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
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" err %lld\n", phb->hose->global_number, pe_no, rc);
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return;
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}
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cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
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bdfn, pe_no, fstate);
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if (fstate != 0) {
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rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
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OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
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if (rc) {
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pr_warning("PCI %d: Failed to clear EEH freeze state"
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" for PE#%d, err %lld\n",
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phb->hose->global_number, pe_no, rc);
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}
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}
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}
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static int pnv_pci_read_config(struct pci_bus *bus,
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unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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struct pnv_phb *phb = hose->private_data;
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u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
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s64 rc;
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (size) {
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case 1: {
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u8 v8;
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rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
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*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
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break;
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}
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case 2: {
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u16 v16;
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rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
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&v16);
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*val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
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break;
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}
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case 4: {
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u32 v32;
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rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
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*val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
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break;
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}
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
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bus->number, devfn, where, size, *val);
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/* Check if the PHB got frozen due to an error (no response) */
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pnv_pci_config_check_eeh(phb, bus, bdfn);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pnv_pci_write_config(struct pci_bus *bus,
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unsigned int devfn,
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int where, int size, u32 val)
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{
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struct pci_controller *hose = pci_bus_to_host(bus);
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struct pnv_phb *phb = hose->private_data;
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u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
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bus->number, devfn, where, size, val);
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switch (size) {
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case 1:
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opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
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break;
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case 2:
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opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
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break;
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case 4:
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opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
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break;
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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/* Check if the PHB got frozen due to an error (no response) */
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pnv_pci_config_check_eeh(phb, bus, bdfn);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops pnv_pci_ops = {
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.read = pnv_pci_read_config,
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.write = pnv_pci_write_config,
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};
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static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
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unsigned long uaddr, enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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u64 proto_tce;
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u64 *tcep;
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u64 rpn;
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proto_tce = TCE_PCI_READ; // Read allowed
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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tcep = ((u64 *)tbl->it_base) + index;
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while (npages--) {
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/* can't move this out since we might cross LMB boundary */
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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*tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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uaddr += TCE_PAGE_SIZE;
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tcep++;
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}
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return 0;
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}
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static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
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{
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u64 *tcep = ((u64 *)tbl->it_base) + index;
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while (npages--)
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*(tcep++) = 0;
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}
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void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
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void *tce_mem, u64 tce_size,
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u64 dma_offset)
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{
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tbl->it_blocksize = 16;
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tbl->it_base = (unsigned long)tce_mem;
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tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
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tbl->it_index = 0;
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tbl->it_size = tce_size >> 3;
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tbl->it_busno = 0;
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tbl->it_type = TCE_PCI;
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}
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static struct iommu_table * __devinit
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pnv_pci_setup_bml_iommu(struct pci_controller *hose)
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{
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struct iommu_table *tbl;
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const __be64 *basep;
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const __be32 *sizep;
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basep = of_get_property(hose->dn, "linux,tce-base", NULL);
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sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
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if (basep == NULL || sizep == NULL) {
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pr_err("PCI: %s has missing tce entries !\n", hose->dn->full_name);
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return NULL;
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}
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tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
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if (WARN_ON(!tbl))
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return NULL;
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pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
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be32_to_cpup(sizep), 0);
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iommu_init_table(tbl, hose->node);
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return tbl;
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}
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static void __devinit pnv_pci_dma_fallback_setup(struct pci_controller *hose,
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struct pci_dev *pdev)
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{
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struct device_node *np = pci_bus_to_OF_node(hose->bus);
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struct pci_dn *pdn;
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if (np == NULL)
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return;
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pdn = PCI_DN(np);
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if (!pdn->iommu_table)
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pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
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if (!pdn->iommu_table)
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return;
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set_iommu_table_base(&pdev->dev, pdn->iommu_table);
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}
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static void __devinit pnv_pci_dma_dev_setup(struct pci_dev *pdev)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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/* If we have no phb structure, try to setup a fallback based on
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* the device-tree (RTAS PCI for example)
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*/
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if (phb && phb->dma_dev_setup)
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phb->dma_dev_setup(phb, pdev);
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else
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pnv_pci_dma_fallback_setup(hose, pdev);
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}
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void __init pnv_pci_init(void)
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{
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struct device_node *np;
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pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN);
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/* We do not want to just probe */
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pci_probe_only = 0;
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/* OPAL absent, try POPAL first then RTAS detection of PHBs */
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if (!firmware_has_feature(FW_FEATURE_OPAL)) {
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#ifdef CONFIG_PPC_POWERNV_RTAS
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init_pci_config_tokens();
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find_and_init_phbs();
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#endif /* CONFIG_PPC_POWERNV_RTAS */
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} else {
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/* OPAL is here, do our normal stuff */
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/* Look for p5ioc2 IO-Hubs */
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for_each_compatible_node(np, NULL, "ibm,p5ioc2")
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pnv_pci_init_p5ioc2_hub(np);
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}
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/* Setup the linkage between OF nodes and PHBs */
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pci_devs_phb_init();
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/* Configure IOMMU DMA hooks */
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ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
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ppc_md.tce_build = pnv_tce_build;
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ppc_md.tce_free = pnv_tce_free;
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set_pci_dma_ops(&dma_iommu_ops);
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}
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