Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next
Freescale updates from Scott: "Highlights include more 8xx optimizations, an e6500 hugetlb optimization, QMan device tree nodes, t1024/t1023 support, and various fixes and cleanup."
This commit is contained in:
Michael Ellerman
@@ -48,6 +48,19 @@
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mtspr spr, reg
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#endif
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/* Macro to test if an address is a kernel address */
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#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
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#define IS_KERNEL(tmp, addr) \
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andis. tmp, addr, 0x8000 /* Address >= 0x80000000 */
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#define BRANCH_UNLESS_KERNEL(label) beq label
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#else
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#define IS_KERNEL(tmp, addr) \
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rlwinm tmp, addr, 16, 16, 31; \
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cmpli cr0, tmp, PAGE_OFFSET >> 16
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#define BRANCH_UNLESS_KERNEL(label) blt label
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#endif
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/*
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* Value for the bits that have fixed value in RPN entries.
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* Also used for tagging DAR for DTLBerror.
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@@ -116,13 +129,13 @@ turn_on_mmu:
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*/
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#define EXCEPTION_PROLOG \
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EXCEPTION_PROLOG_0; \
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mfcr r10; \
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EXCEPTION_PROLOG_1; \
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EXCEPTION_PROLOG_2
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#define EXCEPTION_PROLOG_0 \
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mtspr SPRN_SPRG_SCRATCH0,r10; \
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mtspr SPRN_SPRG_SCRATCH1,r11; \
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mfcr r10
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mtspr SPRN_SPRG_SCRATCH1,r11
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#define EXCEPTION_PROLOG_1 \
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mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
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@@ -162,7 +175,6 @@ turn_on_mmu:
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* Exception exit code.
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*/
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#define EXCEPTION_EPILOG_0 \
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mtcr r10; \
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mfspr r10,SPRN_SPRG_SCRATCH0; \
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mfspr r11,SPRN_SPRG_SCRATCH1
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@@ -297,19 +309,22 @@ SystemCall:
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* We have to use the MD_xxx registers for the tablewalk because the
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* equivalent MI_xxx registers only perform the attribute functions.
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*/
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#ifdef CONFIG_8xx_CPU15
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#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
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addi tmp, addr, PAGE_SIZE; \
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tlbie tmp; \
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addi tmp, addr, -PAGE_SIZE; \
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tlbie tmp
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#else
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#define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
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#endif
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InstructionTLBMiss:
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#ifdef CONFIG_8xx_CPU6
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mtspr SPRN_DAR, r3
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mtspr SPRN_SPRG_SCRATCH2, r3
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#endif
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EXCEPTION_PROLOG_0
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mtspr SPRN_SPRG_SCRATCH2, r10
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mfspr r10, SPRN_SRR0 /* Get effective address of fault */
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#ifdef CONFIG_8xx_CPU15
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addi r11, r10, PAGE_SIZE
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tlbie r11
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addi r11, r10, -PAGE_SIZE
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tlbie r11
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#endif
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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@@ -317,24 +332,34 @@ InstructionTLBMiss:
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#ifdef CONFIG_MODULES
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/* Only modules will cause ITLB Misses as we always
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* pin the first 8MB of kernel memory */
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andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
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#endif
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mfspr r11, SPRN_SRR0 /* Get effective address of fault */
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INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
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mfcr r10
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IS_KERNEL(r11, r11)
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mfspr r11, SPRN_M_TW /* Get level 1 table */
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#ifdef CONFIG_MODULES
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beq 3f
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BRANCH_UNLESS_KERNEL(3f)
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
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3:
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mtcr r10
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mfspr r10, SPRN_SRR0 /* Get effective address of fault */
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#else
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mfspr r10, SPRN_SRR0 /* Get effective address of fault */
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INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
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mfspr r11, SPRN_M_TW /* Get level 1 table base address */
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#endif
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/* Insert level 1 index */
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rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
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/* Load the MI_TWC with the attributes for this "segment." */
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MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
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rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
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/* Extract level 2 index */
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rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
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lwzx r10, r10, r11 /* Get the pte */
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rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
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lwz r10, 0(r10) /* Get the pte */
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/* Insert the APG into the TWC from the Linux PTE. */
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rlwimi r11, r10, 0, 25, 26
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/* Load the MI_TWC with the attributes for this "segment." */
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MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
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#ifdef CONFIG_SWAP
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rlwinm r11, r10, 32-5, _PAGE_PRESENT
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@@ -343,40 +368,41 @@ InstructionTLBMiss:
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#endif
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li r11, RPN_PATTERN
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/* The Linux PTE won't go exactly into the MMU TLB.
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* Software indicator bits 21 and 28 must be clear.
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* Software indicator bits 20-23 and 28 must be clear.
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* Software indicator bits 24, 25, 26, and 27 must be
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* set. All other Linux PTE bits control the behavior
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* of the MMU.
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*/
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rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
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rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */
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MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
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/* Restore registers */
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#ifdef CONFIG_8xx_CPU6
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mfspr r3, SPRN_DAR
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mtspr SPRN_DAR, r11 /* Tag DAR */
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mfspr r3, SPRN_SPRG_SCRATCH2
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#endif
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mfspr r10, SPRN_SPRG_SCRATCH2
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EXCEPTION_EPILOG_0
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rfi
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. = 0x1200
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DataStoreTLBMiss:
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#ifdef CONFIG_8xx_CPU6
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mtspr SPRN_DAR, r3
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mtspr SPRN_SPRG_SCRATCH2, r3
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#endif
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EXCEPTION_PROLOG_0
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mtspr SPRN_SPRG_SCRATCH2, r10
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mfspr r10, SPRN_MD_EPN
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mfcr r10
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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andis. r11, r10, 0x8000
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mfspr r11, SPRN_MD_EPN
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IS_KERNEL(r11, r11)
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mfspr r11, SPRN_M_TW /* Get level 1 table */
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beq 3f
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BRANCH_UNLESS_KERNEL(3f)
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
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3:
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mtcr r10
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mfspr r10, SPRN_MD_EPN
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/* Insert level 1 index */
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rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
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@@ -388,13 +414,13 @@ DataStoreTLBMiss:
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rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
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lwz r10, 0(r10) /* Get the pte */
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/* Insert the Guarded flag into the TWC from the Linux PTE.
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* It is bit 27 of both the Linux PTE and the TWC (at least
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/* Insert the Guarded flag and APG into the TWC from the Linux PTE.
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* It is bit 26-27 of both the Linux PTE and the TWC (at least
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* I got that right :-). It will be better when we can put
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* this into the Linux pgd/pmd and load it in the operation
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* above.
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*/
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rlwimi r11, r10, 0, 27, 27
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rlwimi r11, r10, 0, 26, 27
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/* Insert the WriteThru flag into the TWC from the Linux PTE.
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* It is bit 25 in the Linux PTE and bit 30 in the TWC
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*/
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@@ -423,14 +449,14 @@ DataStoreTLBMiss:
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*/
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li r11, RPN_PATTERN
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rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
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rlwimi r10, r11, 0, 20, 20 /* clear 20 */
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MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
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/* Restore registers */
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#ifdef CONFIG_8xx_CPU6
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mfspr r3, SPRN_DAR
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mfspr r3, SPRN_SPRG_SCRATCH2
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#endif
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mtspr SPRN_DAR, r11 /* Tag DAR */
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mfspr r10, SPRN_SPRG_SCRATCH2
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EXCEPTION_EPILOG_0
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rfi
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@@ -456,6 +482,7 @@ InstructionTLBError:
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. = 0x1400
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DataTLBError:
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EXCEPTION_PROLOG_0
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mfcr r10
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mfspr r11, SPRN_DAR
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cmpwi cr0, r11, RPN_PATTERN
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@@ -503,9 +530,9 @@ FixupDAR:/* Entry point for dcbx workaround. */
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mtspr SPRN_SPRG_SCRATCH2, r10
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/* fetch instruction from memory. */
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mfspr r10, SPRN_SRR0
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andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
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IS_KERNEL(r11, r10)
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mfspr r11, SPRN_M_TW /* Get level 1 table */
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beq 3f
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BRANCH_UNLESS_KERNEL(3f)
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lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
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/* Insert level 1 index */
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3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
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@@ -743,15 +770,20 @@ initial_mmu:
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ori r8, r8, MI_EVALID /* Mark it valid */
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mtspr SPRN_MI_EPN, r8
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mtspr SPRN_MD_EPN, r8
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li r8, MI_PS8MEG /* Set 8M byte page */
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li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */
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ori r8, r8, MI_SVALID /* Make it valid */
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mtspr SPRN_MI_TWC, r8
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li r8, MI_PS8MEG /* Set 8M byte page, APG 0 */
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ori r8, r8, MI_SVALID /* Make it valid */
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mtspr SPRN_MD_TWC, r8
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li r8, MI_BOOTINIT /* Create RPN for address 0 */
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mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
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mtspr SPRN_MD_RPN, r8
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lis r8, MI_Kp@h /* Set the protection mode */
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lis r8, MI_APG_INIT@h /* Set protection modes */
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ori r8, r8, MI_APG_INIT@l
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mtspr SPRN_MI_AP, r8
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lis r8, MD_APG_INIT@h
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ori r8, r8, MD_APG_INIT@l
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mtspr SPRN_MD_AP, r8
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/* Map another 8 MByte at the IMMR to get the processor
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@@ -58,15 +58,6 @@ BEGIN_FTR_SECTION
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mtlr r0
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lis r3,HID0_NAP@h
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END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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BEGIN_FTR_SECTION
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msync
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li r7,L2CSR0_L2FL@l
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mtspr SPRN_L2CSR0,r7
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2:
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mfspr r7,SPRN_L2CSR0
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andi. r4,r7,L2CSR0_L2FL@l
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bne 2b
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END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
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1:
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/* Go to NAP or DOZE now */
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mfspr r4,SPRN_HID0
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