[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Haavard Skinnemoen
committed by
Linus Torvalds
Linus Torvalds
parent
53e62d3aaa
commit
5f97f7f940
171
arch/avr32/mach-at32ap/extint.c
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171
arch/avr32/mach-at32ap/extint.c
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/*
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* External interrupt handling for AT32AP CPUs
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/random.h>
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#include <asm/io.h>
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#include <asm/arch/sm.h>
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#include "sm.h"
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static void eim_ack_irq(unsigned int irq)
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{
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struct at32_sm *sm = get_irq_chip_data(irq);
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sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
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}
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static void eim_mask_irq(unsigned int irq)
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{
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struct at32_sm *sm = get_irq_chip_data(irq);
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sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
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}
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static void eim_mask_ack_irq(unsigned int irq)
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{
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struct at32_sm *sm = get_irq_chip_data(irq);
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sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
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sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
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}
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static void eim_unmask_irq(unsigned int irq)
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{
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struct at32_sm *sm = get_irq_chip_data(irq);
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sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
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}
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static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
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{
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struct at32_sm *sm = get_irq_chip_data(irq);
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unsigned int i = irq - sm->eim_first_irq;
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u32 mode, edge, level;
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unsigned long flags;
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int ret = 0;
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flow_type &= IRQ_TYPE_SENSE_MASK;
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spin_lock_irqsave(&sm->lock, flags);
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mode = sm_readl(sm, EIM_MODE);
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edge = sm_readl(sm, EIM_EDGE);
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level = sm_readl(sm, EIM_LEVEL);
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switch (flow_type) {
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case IRQ_TYPE_LEVEL_LOW:
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mode |= 1 << i;
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level &= ~(1 << i);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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mode |= 1 << i;
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level |= 1 << i;
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break;
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case IRQ_TYPE_EDGE_RISING:
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mode &= ~(1 << i);
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edge |= 1 << i;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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mode &= ~(1 << i);
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edge &= ~(1 << i);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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sm_writel(sm, EIM_MODE, mode);
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sm_writel(sm, EIM_EDGE, edge);
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sm_writel(sm, EIM_LEVEL, level);
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spin_unlock_irqrestore(&sm->lock, flags);
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return ret;
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}
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struct irq_chip eim_chip = {
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.name = "eim",
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.ack = eim_ack_irq,
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.mask = eim_mask_irq,
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.mask_ack = eim_mask_ack_irq,
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.unmask = eim_unmask_irq,
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.set_type = eim_set_irq_type,
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};
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static void demux_eim_irq(unsigned int irq, struct irq_desc *desc,
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struct pt_regs *regs)
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{
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struct at32_sm *sm = desc->handler_data;
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struct irq_desc *ext_desc;
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unsigned long status, pending;
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unsigned int i, ext_irq;
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spin_lock(&sm->lock);
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status = sm_readl(sm, EIM_ISR);
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pending = status & sm_readl(sm, EIM_IMR);
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while (pending) {
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i = fls(pending) - 1;
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pending &= ~(1 << i);
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ext_irq = i + sm->eim_first_irq;
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ext_desc = irq_desc + ext_irq;
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ext_desc->handle_irq(ext_irq, ext_desc, regs);
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}
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spin_unlock(&sm->lock);
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}
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static int __init eim_init(void)
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{
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struct at32_sm *sm = &system_manager;
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unsigned int i;
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unsigned int nr_irqs;
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unsigned int int_irq;
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u32 pattern;
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/*
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* The EIM is really the same module as SM, so register
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* mapping, etc. has been taken care of already.
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*/
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/*
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* Find out how many interrupt lines that are actually
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* implemented in hardware.
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*/
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sm_writel(sm, EIM_IDR, ~0UL);
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sm_writel(sm, EIM_MODE, ~0UL);
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pattern = sm_readl(sm, EIM_MODE);
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nr_irqs = fls(pattern);
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sm->eim_chip = &eim_chip;
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for (i = 0; i < nr_irqs; i++) {
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set_irq_chip(sm->eim_first_irq + i, &eim_chip);
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set_irq_chip_data(sm->eim_first_irq + i, sm);
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}
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int_irq = platform_get_irq_byname(sm->pdev, "eim");
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set_irq_chained_handler(int_irq, demux_eim_irq);
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set_irq_data(int_irq, sm);
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printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
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sm->regs, int_irq);
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printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
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nr_irqs, sm->eim_first_irq);
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return 0;
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}
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arch_initcall(eim_init);
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