Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (116 commits) x86: Enable forced interrupt threading support x86: Mark low level interrupts IRQF_NO_THREAD x86: Use generic show_interrupts x86: ioapic: Avoid redundant lookup of irq_cfg x86: ioapic: Use new move_irq functions x86: Use the proper accessors in fixup_irqs() x86: ioapic: Use irq_data->state x86: ioapic: Simplify irq chip and handler setup x86: Cleanup the genirq name space genirq: Add chip flag to force mask on suspend genirq: Add desc->irq_data accessor genirq: Add comments to Kconfig switches genirq: Fixup fasteoi handler for oneshot mode genirq: Provide forced interrupt threading sched: Switch wait_task_inactive to schedule_hrtimeout() genirq: Add IRQF_NO_THREAD genirq: Allow shared oneshot interrupts genirq: Prepare the handling of shared oneshot interrupts genirq: Make warning in handle_percpu_event useful x86: ioapic: Move trigger defines to io_apic.h ... Fix up trivial(?) conflicts in arch/x86/pci/xen.c due to genirq name space changes clashing with the Xen cleanups. The set_irq_msi() had moved to xen_bind_pirq_msi_to_irq().
This commit is contained in:
Linus Torvalds
@@ -43,6 +43,7 @@
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#include <asm/i8259.h>
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#include <asm/proto.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/desc.h>
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#include <asm/hpet.h>
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#include <asm/idle.h>
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@@ -1209,7 +1210,7 @@ void __cpuinit setup_local_APIC(void)
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rdtscll(tsc);
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if (disable_apic) {
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arch_disable_smp_support();
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disable_ioapic_support();
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return;
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}
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@@ -1448,7 +1449,7 @@ int __init enable_IR(void)
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void __init enable_IR_x2apic(void)
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{
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unsigned long flags;
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struct IO_APIC_route_entry **ioapic_entries = NULL;
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struct IO_APIC_route_entry **ioapic_entries;
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int ret, x2apic_enabled = 0;
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int dmar_table_init_ret;
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@@ -108,7 +108,10 @@ DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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int skip_ioapic_setup;
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void arch_disable_smp_support(void)
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/**
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* disable_ioapic_support() - disables ioapic support at runtime
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*/
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void disable_ioapic_support(void)
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{
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#ifdef CONFIG_PCI
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noioapicquirk = 1;
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@@ -120,11 +123,14 @@ void arch_disable_smp_support(void)
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static int __init parse_noapic(char *str)
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{
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/* disable IO-APIC */
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arch_disable_smp_support();
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disable_ioapic_support();
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return 0;
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}
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early_param("noapic", parse_noapic);
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static int io_apic_setup_irq_pin_once(unsigned int irq, int node,
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struct io_apic_irq_attr *attr);
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/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
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void mp_save_irq(struct mpc_intsrc *m)
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{
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@@ -181,7 +187,7 @@ int __init arch_early_irq_init(void)
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irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
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for (i = 0; i < count; i++) {
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set_irq_chip_data(i, &cfg[i]);
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irq_set_chip_data(i, &cfg[i]);
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zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
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zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
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/*
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@@ -200,7 +206,7 @@ int __init arch_early_irq_init(void)
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#ifdef CONFIG_SPARSE_IRQ
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static struct irq_cfg *irq_cfg(unsigned int irq)
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{
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return get_irq_chip_data(irq);
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return irq_get_chip_data(irq);
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}
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static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
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@@ -226,7 +232,7 @@ static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
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{
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if (!cfg)
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return;
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set_irq_chip_data(at, NULL);
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irq_set_chip_data(at, NULL);
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free_cpumask_var(cfg->domain);
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free_cpumask_var(cfg->old_domain);
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kfree(cfg);
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@@ -256,14 +262,14 @@ static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
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if (res < 0) {
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if (res != -EEXIST)
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return NULL;
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cfg = get_irq_chip_data(at);
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cfg = irq_get_chip_data(at);
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if (cfg)
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return cfg;
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}
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cfg = alloc_irq_cfg(at, node);
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if (cfg)
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set_irq_chip_data(at, cfg);
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irq_set_chip_data(at, cfg);
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else
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irq_free_desc(at);
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return cfg;
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@@ -818,7 +824,7 @@ static int EISA_ELCR(unsigned int irq)
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#define default_MCA_trigger(idx) (1)
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#define default_MCA_polarity(idx) default_ISA_polarity(idx)
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static int MPBIOS_polarity(int idx)
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static int irq_polarity(int idx)
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{
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int bus = mp_irqs[idx].srcbus;
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int polarity;
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@@ -860,7 +866,7 @@ static int MPBIOS_polarity(int idx)
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return polarity;
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}
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static int MPBIOS_trigger(int idx)
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static int irq_trigger(int idx)
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{
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int bus = mp_irqs[idx].srcbus;
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int trigger;
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@@ -932,16 +938,6 @@ static int MPBIOS_trigger(int idx)
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return trigger;
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}
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static inline int irq_polarity(int idx)
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{
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return MPBIOS_polarity(idx);
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}
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static inline int irq_trigger(int idx)
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{
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return MPBIOS_trigger(idx);
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}
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static int pin_2_irq(int idx, int apic, int pin)
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{
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int irq;
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@@ -1189,7 +1185,7 @@ void __setup_vector_irq(int cpu)
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raw_spin_lock(&vector_lock);
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/* Mark the inuse vectors */
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for_each_active_irq(irq) {
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cfg = get_irq_chip_data(irq);
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cfg = irq_get_chip_data(irq);
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if (!cfg)
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continue;
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/*
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@@ -1220,10 +1216,6 @@ void __setup_vector_irq(int cpu)
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static struct irq_chip ioapic_chip;
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static struct irq_chip ir_ioapic_chip;
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#define IOAPIC_AUTO -1
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#define IOAPIC_EDGE 0
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#define IOAPIC_LEVEL 1
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#ifdef CONFIG_X86_32
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static inline int IO_APIC_irq_trigger(int irq)
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{
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@@ -1248,35 +1240,31 @@ static inline int IO_APIC_irq_trigger(int irq)
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}
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#endif
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static void ioapic_register_intr(unsigned int irq, unsigned long trigger)
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static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
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unsigned long trigger)
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{
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struct irq_chip *chip = &ioapic_chip;
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irq_flow_handler_t hdl;
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bool fasteoi;
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if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
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trigger == IOAPIC_LEVEL)
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trigger == IOAPIC_LEVEL) {
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irq_set_status_flags(irq, IRQ_LEVEL);
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else
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fasteoi = true;
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} else {
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irq_clear_status_flags(irq, IRQ_LEVEL);
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if (irq_remapped(get_irq_chip_data(irq))) {
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irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
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if (trigger)
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set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
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handle_fasteoi_irq,
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"fasteoi");
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else
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set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
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handle_edge_irq, "edge");
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return;
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fasteoi = false;
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}
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if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
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trigger == IOAPIC_LEVEL)
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set_irq_chip_and_handler_name(irq, &ioapic_chip,
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handle_fasteoi_irq,
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"fasteoi");
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else
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set_irq_chip_and_handler_name(irq, &ioapic_chip,
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handle_edge_irq, "edge");
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if (irq_remapped(cfg)) {
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irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
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chip = &ir_ioapic_chip;
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fasteoi = trigger != 0;
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}
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hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
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irq_set_chip_and_handler_name(irq, chip, hdl,
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fasteoi ? "fasteoi" : "edge");
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}
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static int setup_ioapic_entry(int apic_id, int irq,
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@@ -1374,7 +1362,7 @@ static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
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return;
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}
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ioapic_register_intr(irq, trigger);
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ioapic_register_intr(irq, cfg, trigger);
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if (irq < legacy_pic->nr_legacy_irqs)
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legacy_pic->mask(irq);
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@@ -1385,33 +1373,26 @@ static struct {
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DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
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} mp_ioapic_routing[MAX_IO_APICS];
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static void __init setup_IO_APIC_irqs(void)
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static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
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{
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int apic_id, pin, idx, irq, notcon = 0;
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int node = cpu_to_node(0);
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struct irq_cfg *cfg;
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if (idx != -1)
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return false;
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apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
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apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
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mp_ioapics[apic_id].apicid, pin);
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return true;
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}
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static void __init __io_apic_setup_irqs(unsigned int apic_id)
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{
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int idx, node = cpu_to_node(0);
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struct io_apic_irq_attr attr;
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unsigned int pin, irq;
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for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
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for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
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idx = find_irq_entry(apic_id, pin, mp_INT);
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if (idx == -1) {
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if (!notcon) {
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notcon = 1;
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apic_printk(APIC_VERBOSE,
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KERN_DEBUG " %d-%d",
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mp_ioapics[apic_id].apicid, pin);
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} else
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apic_printk(APIC_VERBOSE, " %d-%d",
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mp_ioapics[apic_id].apicid, pin);
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if (io_apic_pin_not_connected(idx, apic_id, pin))
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continue;
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}
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if (notcon) {
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apic_printk(APIC_VERBOSE,
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" (apicid-pin) not connected\n");
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notcon = 0;
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}
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irq = pin_2_irq(idx, apic_id, pin);
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@@ -1423,25 +1404,24 @@ static void __init setup_IO_APIC_irqs(void)
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* installed and if it returns 1:
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*/
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if (apic->multi_timer_check &&
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apic->multi_timer_check(apic_id, irq))
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apic->multi_timer_check(apic_id, irq))
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continue;
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cfg = alloc_irq_and_cfg_at(irq, node);
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if (!cfg)
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continue;
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set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
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irq_polarity(idx));
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add_pin_to_irq_node(cfg, node, apic_id, pin);
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/*
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* don't mark it in pin_programmed, so later acpi could
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* set it correctly when irq < 16
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*/
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setup_ioapic_irq(apic_id, pin, irq, cfg, irq_trigger(idx),
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irq_polarity(idx));
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io_apic_setup_irq_pin(irq, node, &attr);
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}
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}
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if (notcon)
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apic_printk(APIC_VERBOSE,
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" (apicid-pin) not connected\n");
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static void __init setup_IO_APIC_irqs(void)
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{
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unsigned int apic_id;
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apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
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for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
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__io_apic_setup_irqs(apic_id);
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}
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/*
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@@ -1452,7 +1432,7 @@ static void __init setup_IO_APIC_irqs(void)
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void setup_IO_APIC_irq_extra(u32 gsi)
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{
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int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
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struct irq_cfg *cfg;
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struct io_apic_irq_attr attr;
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/*
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* Convert 'gsi' to 'ioapic.pin'.
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@@ -1472,21 +1452,10 @@ void setup_IO_APIC_irq_extra(u32 gsi)
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if (apic_id == 0 || irq < NR_IRQS_LEGACY)
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return;
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cfg = alloc_irq_and_cfg_at(irq, node);
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if (!cfg)
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return;
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set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
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irq_polarity(idx));
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add_pin_to_irq_node(cfg, node, apic_id, pin);
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if (test_bit(pin, mp_ioapic_routing[apic_id].pin_programmed)) {
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pr_debug("Pin %d-%d already programmed\n",
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mp_ioapics[apic_id].apicid, pin);
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return;
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}
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set_bit(pin, mp_ioapic_routing[apic_id].pin_programmed);
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setup_ioapic_irq(apic_id, pin, irq, cfg,
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irq_trigger(idx), irq_polarity(idx));
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io_apic_setup_irq_pin_once(irq, node, &attr);
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}
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/*
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@@ -1518,7 +1487,8 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
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* The timer IRQ doesn't have to know that behind the
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* scene we may have a 8259A-master in AEOI mode ...
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*/
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set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
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irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
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"edge");
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/*
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* Add it to the IO-APIC irq-routing table:
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@@ -1625,7 +1595,7 @@ __apicdebuginit(void) print_IO_APIC(void)
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for_each_active_irq(irq) {
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struct irq_pin_list *entry;
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cfg = get_irq_chip_data(irq);
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cfg = irq_get_chip_data(irq);
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if (!cfg)
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continue;
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entry = cfg->irq_2_pin;
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@@ -2391,7 +2361,7 @@ static void irq_complete_move(struct irq_cfg *cfg)
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void irq_force_complete_move(int irq)
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{
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struct irq_cfg *cfg = get_irq_chip_data(irq);
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struct irq_cfg *cfg = irq_get_chip_data(irq);
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if (!cfg)
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return;
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@@ -2405,7 +2375,7 @@ static inline void irq_complete_move(struct irq_cfg *cfg) { }
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static void ack_apic_edge(struct irq_data *data)
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{
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irq_complete_move(data->chip_data);
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move_native_irq(data->irq);
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irq_move_irq(data);
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ack_APIC_irq();
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}
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@@ -2462,7 +2432,7 @@ static void ack_apic_level(struct irq_data *data)
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irq_complete_move(cfg);
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#ifdef CONFIG_GENERIC_PENDING_IRQ
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/* If we are moving the irq we need to mask it */
|
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if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
|
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if (unlikely(irqd_is_setaffinity_pending(data))) {
|
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do_unmask_irq = 1;
|
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mask_ioapic(cfg);
|
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}
|
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@@ -2551,7 +2521,7 @@ static void ack_apic_level(struct irq_data *data)
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* and you can go talk to the chipset vendor about it.
|
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*/
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if (!io_apic_level_ack_pending(cfg))
|
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move_masked_irq(irq);
|
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irq_move_masked_irq(data);
|
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unmask_ioapic(cfg);
|
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}
|
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}
|
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@@ -2614,7 +2584,7 @@ static inline void init_IO_APIC_traps(void)
|
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* 0x80, because int 0x80 is hm, kind of importantish. ;)
|
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*/
|
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for_each_active_irq(irq) {
|
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cfg = get_irq_chip_data(irq);
|
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cfg = irq_get_chip_data(irq);
|
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if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
|
||||
/*
|
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* Hmm.. We don't have an entry for this,
|
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@@ -2625,7 +2595,7 @@ static inline void init_IO_APIC_traps(void)
|
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legacy_pic->make_irq(irq);
|
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else
|
||||
/* Strange. Oh, well.. */
|
||||
set_irq_chip(irq, &no_irq_chip);
|
||||
irq_set_chip(irq, &no_irq_chip);
|
||||
}
|
||||
}
|
||||
}
|
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@@ -2665,7 +2635,7 @@ static struct irq_chip lapic_chip __read_mostly = {
|
||||
static void lapic_register_intr(int irq)
|
||||
{
|
||||
irq_clear_status_flags(irq, IRQ_LEVEL);
|
||||
set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
|
||||
irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
|
||||
"edge");
|
||||
}
|
||||
|
||||
@@ -2749,7 +2719,7 @@ int timer_through_8259 __initdata;
|
||||
*/
|
||||
static inline void __init check_timer(void)
|
||||
{
|
||||
struct irq_cfg *cfg = get_irq_chip_data(0);
|
||||
struct irq_cfg *cfg = irq_get_chip_data(0);
|
||||
int node = cpu_to_node(0);
|
||||
int apic1, pin1, apic2, pin2;
|
||||
unsigned long flags;
|
||||
@@ -3060,7 +3030,7 @@ unsigned int create_irq_nr(unsigned int from, int node)
|
||||
raw_spin_unlock_irqrestore(&vector_lock, flags);
|
||||
|
||||
if (ret) {
|
||||
set_irq_chip_data(irq, cfg);
|
||||
irq_set_chip_data(irq, cfg);
|
||||
irq_clear_status_flags(irq, IRQ_NOREQUEST);
|
||||
} else {
|
||||
free_irq_at(irq, cfg);
|
||||
@@ -3085,7 +3055,7 @@ int create_irq(void)
|
||||
|
||||
void destroy_irq(unsigned int irq)
|
||||
{
|
||||
struct irq_cfg *cfg = get_irq_chip_data(irq);
|
||||
struct irq_cfg *cfg = irq_get_chip_data(irq);
|
||||
unsigned long flags;
|
||||
|
||||
irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
|
||||
@@ -3119,7 +3089,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
|
||||
|
||||
dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
|
||||
|
||||
if (irq_remapped(get_irq_chip_data(irq))) {
|
||||
if (irq_remapped(cfg)) {
|
||||
struct irte irte;
|
||||
int ir_index;
|
||||
u16 sub_handle;
|
||||
@@ -3291,6 +3261,7 @@ static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
|
||||
|
||||
static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
|
||||
{
|
||||
struct irq_chip *chip = &msi_chip;
|
||||
struct msi_msg msg;
|
||||
int ret;
|
||||
|
||||
@@ -3298,14 +3269,15 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
set_irq_msi(irq, msidesc);
|
||||
irq_set_msi_desc(irq, msidesc);
|
||||
write_msi_msg(irq, &msg);
|
||||
|
||||
if (irq_remapped(get_irq_chip_data(irq))) {
|
||||
if (irq_remapped(irq_get_chip_data(irq))) {
|
||||
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
|
||||
set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
|
||||
} else
|
||||
set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
|
||||
chip = &msi_ir_chip;
|
||||
}
|
||||
|
||||
irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
|
||||
|
||||
dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
|
||||
|
||||
@@ -3423,8 +3395,8 @@ int arch_setup_dmar_msi(unsigned int irq)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
dmar_msi_write(irq, &msg);
|
||||
set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
|
||||
"edge");
|
||||
irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
|
||||
"edge");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -3482,6 +3454,7 @@ static struct irq_chip hpet_msi_type = {
|
||||
|
||||
int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
|
||||
{
|
||||
struct irq_chip *chip = &hpet_msi_type;
|
||||
struct msi_msg msg;
|
||||
int ret;
|
||||
|
||||
@@ -3501,15 +3474,12 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
hpet_msi_write(get_irq_data(irq), &msg);
|
||||
hpet_msi_write(irq_get_handler_data(irq), &msg);
|
||||
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
|
||||
if (irq_remapped(get_irq_chip_data(irq)))
|
||||
set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
|
||||
handle_edge_irq, "edge");
|
||||
else
|
||||
set_irq_chip_and_handler_name(irq, &hpet_msi_type,
|
||||
handle_edge_irq, "edge");
|
||||
if (irq_remapped(irq_get_chip_data(irq)))
|
||||
chip = &ir_hpet_msi_type;
|
||||
|
||||
irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -3596,7 +3566,7 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
|
||||
|
||||
write_ht_irq_msg(irq, &msg);
|
||||
|
||||
set_irq_chip_and_handler_name(irq, &ht_irq_chip,
|
||||
irq_set_chip_and_handler_name(irq, &ht_irq_chip,
|
||||
handle_edge_irq, "edge");
|
||||
|
||||
dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
|
||||
@@ -3605,7 +3575,40 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
|
||||
}
|
||||
#endif /* CONFIG_HT_IRQ */
|
||||
|
||||
int __init io_apic_get_redir_entries (int ioapic)
|
||||
int
|
||||
io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
|
||||
{
|
||||
struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
|
||||
int ret;
|
||||
|
||||
if (!cfg)
|
||||
return -EINVAL;
|
||||
ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
|
||||
if (!ret)
|
||||
setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg,
|
||||
attr->trigger, attr->polarity);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int io_apic_setup_irq_pin_once(unsigned int irq, int node,
|
||||
struct io_apic_irq_attr *attr)
|
||||
{
|
||||
unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
|
||||
int ret;
|
||||
|
||||
/* Avoid redundant programming */
|
||||
if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) {
|
||||
pr_debug("Pin %d-%d already programmed\n",
|
||||
mp_ioapics[id].apicid, pin);
|
||||
return 0;
|
||||
}
|
||||
ret = io_apic_setup_irq_pin(irq, node, attr);
|
||||
if (!ret)
|
||||
set_bit(pin, mp_ioapic_routing[id].pin_programmed);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __init io_apic_get_redir_entries(int ioapic)
|
||||
{
|
||||
union IO_APIC_reg_01 reg_01;
|
||||
unsigned long flags;
|
||||
@@ -3659,96 +3662,24 @@ int __init arch_probe_nr_irqs(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
static int __io_apic_set_pci_routing(struct device *dev, int irq,
|
||||
struct io_apic_irq_attr *irq_attr)
|
||||
int io_apic_set_pci_routing(struct device *dev, int irq,
|
||||
struct io_apic_irq_attr *irq_attr)
|
||||
{
|
||||
struct irq_cfg *cfg;
|
||||
int node;
|
||||
int ioapic, pin;
|
||||
int trigger, polarity;
|
||||
|
||||
ioapic = irq_attr->ioapic;
|
||||
if (!IO_APIC_IRQ(irq)) {
|
||||
apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
|
||||
ioapic);
|
||||
irq_attr->ioapic);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (dev)
|
||||
node = dev_to_node(dev);
|
||||
else
|
||||
node = cpu_to_node(0);
|
||||
node = dev ? dev_to_node(dev) : cpu_to_node(0);
|
||||
|
||||
cfg = alloc_irq_and_cfg_at(irq, node);
|
||||
if (!cfg)
|
||||
return 0;
|
||||
|
||||
pin = irq_attr->ioapic_pin;
|
||||
trigger = irq_attr->trigger;
|
||||
polarity = irq_attr->polarity;
|
||||
|
||||
/*
|
||||
* IRQs < 16 are already in the irq_2_pin[] map
|
||||
*/
|
||||
if (irq >= legacy_pic->nr_legacy_irqs) {
|
||||
if (__add_pin_to_irq_node(cfg, node, ioapic, pin)) {
|
||||
printk(KERN_INFO "can not add pin %d for irq %d\n",
|
||||
pin, irq);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
setup_ioapic_irq(ioapic, pin, irq, cfg, trigger, polarity);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int io_apic_set_pci_routing(struct device *dev, int irq,
|
||||
struct io_apic_irq_attr *irq_attr)
|
||||
{
|
||||
int ioapic, pin;
|
||||
/*
|
||||
* Avoid pin reprogramming. PRTs typically include entries
|
||||
* with redundant pin->gsi mappings (but unique PCI devices);
|
||||
* we only program the IOAPIC on the first.
|
||||
*/
|
||||
ioapic = irq_attr->ioapic;
|
||||
pin = irq_attr->ioapic_pin;
|
||||
if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
|
||||
pr_debug("Pin %d-%d already programmed\n",
|
||||
mp_ioapics[ioapic].apicid, pin);
|
||||
return 0;
|
||||
}
|
||||
set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
|
||||
|
||||
return __io_apic_set_pci_routing(dev, irq, irq_attr);
|
||||
}
|
||||
|
||||
u8 __init io_apic_unique_id(u8 id)
|
||||
{
|
||||
#ifdef CONFIG_X86_32
|
||||
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
|
||||
!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
|
||||
return io_apic_get_unique_id(nr_ioapics, id);
|
||||
else
|
||||
return id;
|
||||
#else
|
||||
int i;
|
||||
DECLARE_BITMAP(used, 256);
|
||||
|
||||
bitmap_zero(used, 256);
|
||||
for (i = 0; i < nr_ioapics; i++) {
|
||||
struct mpc_ioapic *ia = &mp_ioapics[i];
|
||||
__set_bit(ia->apicid, used);
|
||||
}
|
||||
if (!test_bit(id, used))
|
||||
return id;
|
||||
return find_first_zero_bit(used, 256);
|
||||
#endif
|
||||
return io_apic_setup_irq_pin_once(irq, node, irq_attr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
int __init io_apic_get_unique_id(int ioapic, int apic_id)
|
||||
static int __init io_apic_get_unique_id(int ioapic, int apic_id)
|
||||
{
|
||||
union IO_APIC_reg_00 reg_00;
|
||||
static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
|
||||
@@ -3821,9 +3752,33 @@ int __init io_apic_get_unique_id(int ioapic, int apic_id)
|
||||
|
||||
return apic_id;
|
||||
}
|
||||
|
||||
static u8 __init io_apic_unique_id(u8 id)
|
||||
{
|
||||
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
|
||||
!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
|
||||
return io_apic_get_unique_id(nr_ioapics, id);
|
||||
else
|
||||
return id;
|
||||
}
|
||||
#else
|
||||
static u8 __init io_apic_unique_id(u8 id)
|
||||
{
|
||||
int i;
|
||||
DECLARE_BITMAP(used, 256);
|
||||
|
||||
bitmap_zero(used, 256);
|
||||
for (i = 0; i < nr_ioapics; i++) {
|
||||
struct mpc_ioapic *ia = &mp_ioapics[i];
|
||||
__set_bit(ia->apicid, used);
|
||||
}
|
||||
if (!test_bit(id, used))
|
||||
return id;
|
||||
return find_first_zero_bit(used, 256);
|
||||
}
|
||||
#endif
|
||||
|
||||
int __init io_apic_get_version(int ioapic)
|
||||
static int __init io_apic_get_version(int ioapic)
|
||||
{
|
||||
union IO_APIC_reg_01 reg_01;
|
||||
unsigned long flags;
|
||||
@@ -3868,8 +3823,8 @@ int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
|
||||
void __init setup_ioapic_dest(void)
|
||||
{
|
||||
int pin, ioapic, irq, irq_entry;
|
||||
struct irq_desc *desc;
|
||||
const struct cpumask *mask;
|
||||
struct irq_data *idata;
|
||||
|
||||
if (skip_ioapic_setup == 1)
|
||||
return;
|
||||
@@ -3884,21 +3839,20 @@ void __init setup_ioapic_dest(void)
|
||||
if ((ioapic > 0) && (irq > 16))
|
||||
continue;
|
||||
|
||||
desc = irq_to_desc(irq);
|
||||
idata = irq_get_irq_data(irq);
|
||||
|
||||
/*
|
||||
* Honour affinities which have been set in early boot
|
||||
*/
|
||||
if (desc->status &
|
||||
(IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
|
||||
mask = desc->irq_data.affinity;
|
||||
if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
|
||||
mask = idata->affinity;
|
||||
else
|
||||
mask = apic->target_cpus();
|
||||
|
||||
if (intr_remapping_enabled)
|
||||
ir_ioapic_set_affinity(&desc->irq_data, mask, false);
|
||||
ir_ioapic_set_affinity(idata, mask, false);
|
||||
else
|
||||
ioapic_set_affinity(&desc->irq_data, mask, false);
|
||||
ioapic_set_affinity(idata, mask, false);
|
||||
}
|
||||
|
||||
}
|
||||
@@ -4026,7 +3980,7 @@ int mp_find_ioapic_pin(int ioapic, u32 gsi)
|
||||
return gsi - mp_gsi_routing[ioapic].gsi_base;
|
||||
}
|
||||
|
||||
static int bad_ioapic(unsigned long address)
|
||||
static __init int bad_ioapic(unsigned long address)
|
||||
{
|
||||
if (nr_ioapics >= MAX_IO_APICS) {
|
||||
printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
|
||||
@@ -4086,20 +4040,16 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
|
||||
/* Enable IOAPIC early just for system timer */
|
||||
void __init pre_init_apic_IRQ0(void)
|
||||
{
|
||||
struct irq_cfg *cfg;
|
||||
struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
|
||||
|
||||
printk(KERN_INFO "Early APIC setup for system timer0\n");
|
||||
#ifndef CONFIG_SMP
|
||||
physid_set_mask_of_physid(boot_cpu_physical_apicid,
|
||||
&phys_cpu_present_map);
|
||||
#endif
|
||||
/* Make sure the irq descriptor is set up */
|
||||
cfg = alloc_irq_and_cfg_at(0, 0);
|
||||
|
||||
setup_local_APIC();
|
||||
|
||||
add_pin_to_irq_node(cfg, 0, 0, 0);
|
||||
set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
|
||||
|
||||
setup_ioapic_irq(0, 0, 0, cfg, 0, 0);
|
||||
io_apic_setup_irq_pin(0, 0, &attr);
|
||||
irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
|
||||
"edge");
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user