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[ARM] fixmap support

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This is the minimum fixmap interface expected to be implemented by
architectures supporting highmem.

We have a second level page table already allocated and covering
0xfff00000-0xffffffff because the exception vector page is located
at 0xffff0000, and various cache tricks already use some entries above
0xffff0000.  Therefore the PTEs covering 0xfff00000-0xfffeffff are free
to be used.

However the XScale cache flushing code already uses virtual addresses
between 0xfffe0000 and 0xfffeffff.

So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff.

The Documentation/arm/memory.txt information is updated accordingly,
including the information about the actual top of DMA memory mapping
region which didn't match the code.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Nicolas Pitre
2008-09-16 13:05:53 -04:00
parent 1522ac3ec9
commit 5f0fbf9eca
3 changed files with 50 additions and 3 deletions
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3
arch/arm/mm/mm.h
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@@ -1,7 +1,6 @@
/* the upper-most page table pointer */
#ifdef CONFIG_MMU
/* the upper-most page table pointer */
extern pmd_t *top_pmd;
#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)