Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts: drivers/net/ethernet/altera/altera_sgdma.c net/netlink/af_netlink.c net/sched/cls_api.c net/sched/sch_api.c The netlink conflict dealt with moving to netlink_capable() and netlink_ns_capable() in the 'net' tree vs. supporting 'tc' operations in non-init namespaces. These were simple transformations from netlink_capable to netlink_ns_capable. The Altera driver conflict was simply code removal overlapping some void pointer cast cleanups in net-next. Signed-off-by: David S. Miller <davem@davemloft.net>
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@@ -186,7 +186,7 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
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{
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u16 phy_reg = 0;
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u32 phy_id = 0;
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s32 ret_val;
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s32 ret_val = 0;
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u16 retry_count;
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u32 mac_reg = 0;
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@@ -217,11 +217,13 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
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/* In case the PHY needs to be in mdio slow mode,
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* set slow mode and try to get the PHY id again.
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*/
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hw->phy.ops.release(hw);
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ret_val = e1000_set_mdio_slow_mode_hv(hw);
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if (!ret_val)
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ret_val = e1000e_get_phy_id(hw);
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hw->phy.ops.acquire(hw);
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if (hw->mac.type < e1000_pch_lpt) {
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hw->phy.ops.release(hw);
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ret_val = e1000_set_mdio_slow_mode_hv(hw);
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if (!ret_val)
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ret_val = e1000e_get_phy_id(hw);
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hw->phy.ops.acquire(hw);
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}
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if (ret_val)
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return false;
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@@ -842,6 +844,17 @@ s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
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}
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}
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if (hw->phy.type == e1000_phy_82579) {
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ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
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&data);
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if (ret_val)
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goto release;
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data &= ~I82579_LPI_100_PLL_SHUT;
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ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
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data);
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}
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/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
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ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
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if (ret_val)
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@@ -1314,15 +1327,18 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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return ret_val;
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}
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/* When connected at 10Mbps half-duplex, 82579 parts are excessively
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/* When connected at 10Mbps half-duplex, some parts are excessively
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* aggressive resulting in many collisions. To avoid this, increase
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* the IPG and reduce Rx latency in the PHY.
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*/
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if ((hw->mac.type == e1000_pch2lan) && link) {
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if (((hw->mac.type == e1000_pch2lan) ||
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(hw->mac.type == e1000_pch_lpt)) && link) {
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u32 reg;
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reg = er32(STATUS);
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if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
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u16 emi_addr;
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reg = er32(TIPG);
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reg &= ~E1000_TIPG_IPGT_MASK;
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reg |= 0xFF;
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@@ -1333,8 +1349,12 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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ret_val =
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e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
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if (hw->mac.type == e1000_pch2lan)
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emi_addr = I82579_RX_CONFIG;
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else
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emi_addr = I217_RX_CONFIG;
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ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
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hw->phy.ops.release(hw);
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@@ -2494,51 +2514,44 @@ release:
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* e1000_k1_gig_workaround_lv - K1 Si workaround
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* @hw: pointer to the HW structure
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*
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* Workaround to set the K1 beacon duration for 82579 parts
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* Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
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* Disable K1 in 1000Mbps and 100Mbps
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**/
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static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
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{
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s32 ret_val = 0;
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u16 status_reg = 0;
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u32 mac_reg;
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u16 phy_reg;
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if (hw->mac.type != e1000_pch2lan)
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return 0;
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/* Set K1 beacon duration based on 1Gbps speed or otherwise */
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/* Set K1 beacon duration based on 10Mbs speed */
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ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
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if (ret_val)
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return ret_val;
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if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
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== (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
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mac_reg = er32(FEXTNVM4);
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mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
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ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
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if (ret_val)
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return ret_val;
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if (status_reg & HV_M_STATUS_SPEED_1000) {
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if (status_reg &
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(HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
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u16 pm_phy_reg;
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mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
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phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
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/* LV 1G Packet drop issue wa */
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/* LV 1G/100 Packet drop issue wa */
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ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
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if (ret_val)
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return ret_val;
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pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
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pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
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ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
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if (ret_val)
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return ret_val;
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} else {
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u32 mac_reg;
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mac_reg = er32(FEXTNVM4);
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mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
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mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
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phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
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ew32(FEXTNVM4, mac_reg);
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}
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ew32(FEXTNVM4, mac_reg);
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ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
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}
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return ret_val;
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