drm/amd/amdgpu: add SI defines/registers
Add missing gca MMIO registers and defines necessary for the next patch which re-works a lot of gfx v6 to use the new SI headers. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher

szülő
de2bdb3dcf
commit
5e2e211995
@@ -1757,4 +1757,28 @@
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#define mmVGT_VTX_CNT_EN 0xA2AE
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#define mmVGT_VTX_VECT_EJECT_REG 0x222C
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/* manually added from old sid.h */
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#define mmCB_PERFCOUNTER0_SELECT0 0x2688
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#define mmCB_PERFCOUNTER1_SELECT0 0x268A
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#define mmCB_PERFCOUNTER1_SELECT1 0x268B
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#define mmCB_PERFCOUNTER2_SELECT0 0x268C
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#define mmCB_PERFCOUNTER2_SELECT1 0x268D
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#define mmCB_PERFCOUNTER3_SELECT0 0x268E
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#define mmCB_PERFCOUNTER3_SELECT1 0x268F
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#define mmCP_COHER_CNTL2 0x217A
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#define mmCP_DEBUG 0x307F
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#define mmRLC_SERDES_MASTER_BUSY_0 0x3119
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#define mmRLC_SERDES_MASTER_BUSY_1 0x311A
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#define mmRLC_RL_BASE 0x30C1
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#define mmRLC_RL_SIZE 0x30C2
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#define mmRLC_UCODE_ADDR 0x30CB
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#define mmRLC_UCODE_DATA 0x30CC
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#define mmRLC_GCPM_GENERAL_3 0x311E
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#define mmRLC_SERDES_WR_MASTER_MASK_0 0x3115
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#define mmRLC_SERDES_WR_MASTER_MASK_1 0x3116
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#define mmRLC_TTOP_D 0x3105
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#define mmRLC_CLEAR_STATE_RESTORE_BASE 0x30C8
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#define mmRLC_PG_AO_CU_MASK 0x310B
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#define mmSPI_STATIC_THREAD_MGMT_3 0x243A
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#endif
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@@ -269,4 +269,7 @@
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#define mmVCE_CONFIG 0x0F94
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#define mmXDMA_MSTR_MEM_OVERFLOW_CNTL 0x03F8
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/* from the old sid.h */
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#define mmDMA_TILING_CONFIG 0x342E
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#endif
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