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clk: tegra: Fix xusb_hs_src clock hierarchy

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Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock.  It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M.  Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Andrew Bresticker
2014-05-14 17:32:59 -07:00
committed by Mike Turquette
parent 9d61707b1f
commit 5c992afcf8
6 changed files with 21 additions and 22 deletions
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3
include/dt-bindings/clock/tegra114-car.h
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@@ -337,6 +337,7 @@
#define TEGRA114_CLK_CLK_OUT_3_MUX 308
#define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_CLK_MAX 311
#define TEGRA114_CLK_XUSB_SS_DIV2 311
#define TEGRA114_CLK_CLK_MAX 312
#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */

3
include/dt-bindings/clock/tegra124-car.h
View File

@@ -336,6 +336,7 @@
#define TEGRA124_CLK_DSIA_MUX 309
#define TEGRA124_CLK_DSIB_MUX 310
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_CLK_MAX 312
#define TEGRA124_CLK_XUSB_SS_DIV2 312
#define TEGRA124_CLK_CLK_MAX 313
#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */