MIPS: Platform files for XLR/XLS processor support
* include/asm/netlogic added with files common for all Netlogic processors (common with XLP which will be added later) * include/asm/netlogic/xlr for XLR/XLS chip specific files * netlogic/xlr for XLR/XLS platform files Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2334/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jayachandran C
committed by
Ralf Baechle
Ralf Baechle
parent
efa0f81c11
commit
5c64250674
73
arch/mips/include/asm/netlogic/xlr/gpio.h
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73
arch/mips/include/asm/netlogic/xlr/gpio.h
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@@ -0,0 +1,73 @@
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
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||||
* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_NLM_GPIO_H
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#define _ASM_NLM_GPIO_H
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#define NETLOGIC_GPIO_INT_EN_REG 0
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#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1
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#define NETLOGIC_GPIO_IO_DIR_REG 2
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#define NETLOGIC_GPIO_IO_DATA_WR_REG 3
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#define NETLOGIC_GPIO_IO_DATA_RD_REG 4
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#define NETLOGIC_GPIO_SWRESET_REG 8
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#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9
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#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10
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#define NETLOGIC_GPIO_DRAM1_RESET_REG 11
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#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12
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#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13
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#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14
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#define NETLOGIC_GPIO_DRAM2_RESET_REG 15
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#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16
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#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21
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#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24
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#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25
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#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26
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#define NETLOGIC_GPIO_FUSE_BANK_REG 35
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#define NETLOGIC_GPIO_CPU_RESET_REG 40
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#define NETLOGIC_GPIO_RNG_REG 43
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#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17
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#define NETLOGIC_GPIO_LED_BITMAP 0x1700000
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#define NETLOGIC_GPIO_LED_0_SHIFT 20
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#define NETLOGIC_GPIO_LED_1_SHIFT 24
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#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01
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#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
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#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
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#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04
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#endif
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131
arch/mips/include/asm/netlogic/xlr/iomap.h
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131
arch/mips/include/asm/netlogic/xlr/iomap.h
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@@ -0,0 +1,131 @@
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_NLM_IOMAP_H
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#define _ASM_NLM_IOMAP_H
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#define DEFAULT_NETLOGIC_IO_BASE CKSEG1ADDR(0x1ef00000)
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#define NETLOGIC_IO_DDR2_CHN0_OFFSET 0x01000
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#define NETLOGIC_IO_DDR2_CHN1_OFFSET 0x02000
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#define NETLOGIC_IO_DDR2_CHN2_OFFSET 0x03000
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#define NETLOGIC_IO_DDR2_CHN3_OFFSET 0x04000
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#define NETLOGIC_IO_PIC_OFFSET 0x08000
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#define NETLOGIC_IO_UART_0_OFFSET 0x14000
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#define NETLOGIC_IO_UART_1_OFFSET 0x15100
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#define NETLOGIC_IO_SIZE 0x1000
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#define NETLOGIC_IO_BRIDGE_OFFSET 0x00000
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#define NETLOGIC_IO_RLD2_CHN0_OFFSET 0x05000
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#define NETLOGIC_IO_RLD2_CHN1_OFFSET 0x06000
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#define NETLOGIC_IO_SRAM_OFFSET 0x07000
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#define NETLOGIC_IO_PCIX_OFFSET 0x09000
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#define NETLOGIC_IO_HT_OFFSET 0x0A000
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#define NETLOGIC_IO_SECURITY_OFFSET 0x0B000
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#define NETLOGIC_IO_GMAC_0_OFFSET 0x0C000
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#define NETLOGIC_IO_GMAC_1_OFFSET 0x0D000
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#define NETLOGIC_IO_GMAC_2_OFFSET 0x0E000
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#define NETLOGIC_IO_GMAC_3_OFFSET 0x0F000
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/* XLS devices */
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#define NETLOGIC_IO_GMAC_4_OFFSET 0x20000
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#define NETLOGIC_IO_GMAC_5_OFFSET 0x21000
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#define NETLOGIC_IO_GMAC_6_OFFSET 0x22000
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#define NETLOGIC_IO_GMAC_7_OFFSET 0x23000
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#define NETLOGIC_IO_PCIE_0_OFFSET 0x1E000
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#define NETLOGIC_IO_PCIE_1_OFFSET 0x1F000
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#define NETLOGIC_IO_SRIO_0_OFFSET 0x1E000
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#define NETLOGIC_IO_SRIO_1_OFFSET 0x1F000
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#define NETLOGIC_IO_USB_0_OFFSET 0x24000
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#define NETLOGIC_IO_USB_1_OFFSET 0x25000
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#define NETLOGIC_IO_COMP_OFFSET 0x1D000
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/* end XLS devices */
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/* XLR devices */
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#define NETLOGIC_IO_SPI4_0_OFFSET 0x10000
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#define NETLOGIC_IO_XGMAC_0_OFFSET 0x11000
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#define NETLOGIC_IO_SPI4_1_OFFSET 0x12000
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#define NETLOGIC_IO_XGMAC_1_OFFSET 0x13000
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/* end XLR devices */
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#define NETLOGIC_IO_I2C_0_OFFSET 0x16000
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#define NETLOGIC_IO_I2C_1_OFFSET 0x17000
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#define NETLOGIC_IO_GPIO_OFFSET 0x18000
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#define NETLOGIC_IO_FLASH_OFFSET 0x19000
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#define NETLOGIC_IO_TB_OFFSET 0x1C000
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#define NETLOGIC_CPLD_OFFSET KSEG1ADDR(0x1d840000)
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/*
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* Base Address (Virtual) of the PCI Config address space
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* For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
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* Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
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* ie 1<<24 = 16M
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*/
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#define DEFAULT_PCI_CONFIG_BASE 0x18000000
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#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
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#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/byteorder.h>
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typedef volatile __u32 nlm_reg_t;
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extern unsigned long netlogic_io_base;
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/* FIXME read once in write_reg */
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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#define netlogic_read_reg(base, offset) ((base)[(offset)])
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#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
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#else
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#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
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#define netlogic_write_reg(base, offset, value) \
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((base)[(offset)] = cpu_to_be32((value)))
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#endif
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#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
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#define netlogic_write_reg_le32(base, offset, value) \
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((base)[(offset)] = cpu_to_le32((value)))
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#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
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#endif /* __ASSEMBLY__ */
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#endif
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231
arch/mips/include/asm/netlogic/xlr/pic.h
Normal file
231
arch/mips/include/asm/netlogic/xlr/pic.h
Normal file
@@ -0,0 +1,231 @@
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/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
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||||
* license below:
|
||||
*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
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||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_NLM_XLR_PIC_H
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#define _ASM_NLM_XLR_PIC_H
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#define PIC_CLKS_PER_SEC 66666666ULL
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/* PIC hardware interrupt numbers */
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#define PIC_IRT_WD_INDEX 0
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#define PIC_IRT_TIMER_0_INDEX 1
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#define PIC_IRT_TIMER_1_INDEX 2
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#define PIC_IRT_TIMER_2_INDEX 3
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#define PIC_IRT_TIMER_3_INDEX 4
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#define PIC_IRT_TIMER_4_INDEX 5
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#define PIC_IRT_TIMER_5_INDEX 6
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#define PIC_IRT_TIMER_6_INDEX 7
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#define PIC_IRT_TIMER_7_INDEX 8
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#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
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#define PIC_IRT_UART_0_INDEX 9
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#define PIC_IRT_UART_1_INDEX 10
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#define PIC_IRT_I2C_0_INDEX 11
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#define PIC_IRT_I2C_1_INDEX 12
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#define PIC_IRT_PCMCIA_INDEX 13
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#define PIC_IRT_GPIO_INDEX 14
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#define PIC_IRT_HYPER_INDEX 15
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#define PIC_IRT_PCIX_INDEX 16
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/* XLS */
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#define PIC_IRT_CDE_INDEX 15
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#define PIC_IRT_BRIDGE_TB_XLS_INDEX 16
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/* XLS */
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#define PIC_IRT_GMAC0_INDEX 17
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#define PIC_IRT_GMAC1_INDEX 18
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#define PIC_IRT_GMAC2_INDEX 19
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#define PIC_IRT_GMAC3_INDEX 20
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#define PIC_IRT_XGS0_INDEX 21
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#define PIC_IRT_XGS1_INDEX 22
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#define PIC_IRT_HYPER_FATAL_INDEX 23
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#define PIC_IRT_PCIX_FATAL_INDEX 24
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#define PIC_IRT_BRIDGE_AERR_INDEX 25
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#define PIC_IRT_BRIDGE_BERR_INDEX 26
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#define PIC_IRT_BRIDGE_TB_XLR_INDEX 27
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#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
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/* XLS */
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#define PIC_IRT_GMAC4_INDEX 21
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#define PIC_IRT_GMAC5_INDEX 22
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#define PIC_IRT_GMAC6_INDEX 23
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#define PIC_IRT_GMAC7_INDEX 24
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#define PIC_IRT_BRIDGE_ERR_INDEX 25
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#define PIC_IRT_PCIE_LINK0_INDEX 26
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#define PIC_IRT_PCIE_LINK1_INDEX 27
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#define PIC_IRT_PCIE_LINK2_INDEX 23
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#define PIC_IRT_PCIE_LINK3_INDEX 24
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#define PIC_IRT_PCIE_XLSB0_LINK2_INDEX 28
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#define PIC_IRT_PCIE_XLSB0_LINK3_INDEX 29
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#define PIC_IRT_SRIO_LINK0_INDEX 26
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#define PIC_IRT_SRIO_LINK1_INDEX 27
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#define PIC_IRT_SRIO_LINK2_INDEX 28
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#define PIC_IRT_SRIO_LINK3_INDEX 29
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#define PIC_IRT_PCIE_INT_INDEX 28
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#define PIC_IRT_PCIE_FATAL_INDEX 29
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#define PIC_IRT_GPIO_B_INDEX 30
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#define PIC_IRT_USB_INDEX 31
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/* XLS */
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#define PIC_NUM_IRTS 32
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#define PIC_CLOCK_TIMER 7
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/* PIC Registers */
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#define PIC_CTRL 0x00
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#define PIC_IPI 0x04
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#define PIC_INT_ACK 0x06
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#define WD_MAX_VAL_0 0x08
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#define WD_MAX_VAL_1 0x09
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#define WD_MASK_0 0x0a
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#define WD_MASK_1 0x0b
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#define WD_HEARBEAT_0 0x0c
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#define WD_HEARBEAT_1 0x0d
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#define PIC_IRT_0_BASE 0x40
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#define PIC_IRT_1_BASE 0x80
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#define PIC_TIMER_MAXVAL_0_BASE 0x100
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#define PIC_TIMER_MAXVAL_1_BASE 0x110
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#define PIC_TIMER_COUNT_0_BASE 0x120
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#define PIC_TIMER_COUNT_1_BASE 0x130
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#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
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#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
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#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
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#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i))
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#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i))
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#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
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/*
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* Mapping between hardware interrupt numbers and IRQs on CPU
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* we use a simple scheme to map PIC interrupts 0-31 to IRQs
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* 8-39. This leaves the IRQ 0-7 for cpu interrupts like
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* count/compare and FMN
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*/
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#define PIC_IRQ_BASE 8
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#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
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#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
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#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
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#define PIC_WD_IRQ PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
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#define PIC_TIMER_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_0_INDEX)
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#define PIC_TIMER_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_1_INDEX)
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#define PIC_TIMER_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_2_INDEX)
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#define PIC_TIMER_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_3_INDEX)
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#define PIC_TIMER_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_4_INDEX)
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#define PIC_TIMER_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_5_INDEX)
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#define PIC_TIMER_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_6_INDEX)
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#define PIC_TIMER_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_TIMER_7_INDEX)
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#define PIC_CLOCK_IRQ (PIC_TIMER_7_IRQ)
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#define PIC_UART_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_0_INDEX)
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#define PIC_UART_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_UART_1_INDEX)
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#define PIC_I2C_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_0_INDEX)
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#define PIC_I2C_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_I2C_1_INDEX)
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#define PIC_PCMCIA_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCMCIA_INDEX)
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#define PIC_GPIO_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_INDEX)
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#define PIC_HYPER_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_INDEX)
|
||||
#define PIC_PCIX_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_INDEX)
|
||||
/* XLS */
|
||||
#define PIC_CDE_IRQ PIC_INTR_TO_IRQ(PIC_IRT_CDE_INDEX)
|
||||
#define PIC_BRIDGE_TB_XLS_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLS_INDEX)
|
||||
/* end XLS */
|
||||
#define PIC_GMAC_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC0_INDEX)
|
||||
#define PIC_GMAC_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC1_INDEX)
|
||||
#define PIC_GMAC_2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC2_INDEX)
|
||||
#define PIC_GMAC_3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC3_INDEX)
|
||||
#define PIC_XGS_0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS0_INDEX)
|
||||
#define PIC_XGS_1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_XGS1_INDEX)
|
||||
#define PIC_HYPER_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_HYPER_FATAL_INDEX)
|
||||
#define PIC_PCIX_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIX_FATAL_INDEX)
|
||||
#define PIC_BRIDGE_AERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
|
||||
#define PIC_BRIDGE_BERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
|
||||
#define PIC_BRIDGE_TB_XLR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
|
||||
#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
|
||||
/* XLS defines */
|
||||
#define PIC_GMAC_4_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
|
||||
#define PIC_GMAC_5_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
|
||||
#define PIC_GMAC_6_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC6_INDEX)
|
||||
#define PIC_GMAC_7_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GMAC7_INDEX)
|
||||
#define PIC_BRIDGE_ERR_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_ERR_INDEX)
|
||||
#define PIC_PCIE_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK0_INDEX)
|
||||
#define PIC_PCIE_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK1_INDEX)
|
||||
#define PIC_PCIE_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK2_INDEX)
|
||||
#define PIC_PCIE_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_LINK3_INDEX)
|
||||
#define PIC_PCIE_XLSB0_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK2_INDEX)
|
||||
#define PIC_PCIE_XLSB0_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_XLSB0_LINK3_INDEX)
|
||||
#define PIC_SRIO_LINK0_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK0_INDEX)
|
||||
#define PIC_SRIO_LINK1_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK1_INDEX)
|
||||
#define PIC_SRIO_LINK2_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK2_INDEX)
|
||||
#define PIC_SRIO_LINK3_IRQ PIC_INTR_TO_IRQ(PIC_IRT_SRIO_LINK3_INDEX)
|
||||
#define PIC_PCIE_INT_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_INT__INDEX)
|
||||
#define PIC_PCIE_FATAL_IRQ PIC_INTR_TO_IRQ(PIC_IRT_PCIE_FATAL_INDEX)
|
||||
#define PIC_GPIO_B_IRQ PIC_INTR_TO_IRQ(PIC_IRT_GPIO_B_INDEX)
|
||||
#define PIC_USB_IRQ PIC_INTR_TO_IRQ(PIC_IRT_USB_INDEX)
|
||||
#define PIC_IRT_LAST_IRQ PIC_USB_IRQ
|
||||
/* end XLS */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
static inline void pic_send_ipi(u32 ipi)
|
||||
{
|
||||
nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
|
||||
|
||||
netlogic_write_reg(mmio, PIC_IPI, ipi);
|
||||
}
|
||||
|
||||
static inline u32 pic_read_control(void)
|
||||
{
|
||||
nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
|
||||
|
||||
return netlogic_read_reg(mmio, PIC_CTRL);
|
||||
}
|
||||
|
||||
static inline void pic_write_control(u32 control)
|
||||
{
|
||||
nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
|
||||
|
||||
netlogic_write_reg(mmio, PIC_CTRL, control);
|
||||
}
|
||||
|
||||
static inline void pic_update_control(u32 control)
|
||||
{
|
||||
nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
|
||||
|
||||
netlogic_write_reg(mmio, PIC_CTRL,
|
||||
(control | netlogic_read_reg(mmio, PIC_CTRL)));
|
||||
}
|
||||
|
||||
#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
|
||||
((irq) <= PIC_TIMER_7_IRQ))
|
||||
#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
|
||||
((irq) <= PIC_IRT_LAST_IRQ))
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_NLM_XLR_PIC_H */
|
||||
54
arch/mips/include/asm/netlogic/xlr/xlr.h
Normal file
54
arch/mips/include/asm/netlogic/xlr/xlr.h
Normal file
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_NLM_XLR_H
|
||||
#define _ASM_NLM_XLR_H
|
||||
|
||||
/* Platform UART functions */
|
||||
struct uart_port;
|
||||
unsigned int nlm_xlr_uart_in(struct uart_port *, int);
|
||||
void nlm_xlr_uart_out(struct uart_port *, int, int);
|
||||
|
||||
/* SMP support functions */
|
||||
void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
|
||||
void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
|
||||
int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
|
||||
void nlm_smp_irq_init(void);
|
||||
void nlm_boot_smp_nmi(void);
|
||||
void prom_pre_boot_secondary_cpus(void);
|
||||
|
||||
extern struct plat_smp_ops nlm_smp_ops;
|
||||
extern unsigned long nlm_common_ebase;
|
||||
|
||||
#endif /* _ASM_NLM_XLR_H */
|
||||
Reference in New Issue
Block a user