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rtlwifi: rtl8192se: Updates from latest Realtek driver version - Part II

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This patch incorporate the differences between the 06/20/2011 and
08/16/2011 Realtek releases of the rtl8192se driver.

The changes include:

1. Fixing some typos in register usage.
2. A change in the handling of decryption status for 802.11w packets.

Signed-off-by: Chaoming Li <chaoming_li@realsil.com.cn>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Chaoming Li
2011-10-12 15:59:09 -05:00
committed by John W. Linville
parent db75993913
commit 5c079d8848
5 changed files with 48 additions and 33 deletions
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22
drivers/net/wireless/rtlwifi/rtl8192se/hw.c
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@@ -1382,7 +1382,7 @@ static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
/* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
tmpu1b = rtl_read_byte(rtlpriv, SYS_FUNC_EN + 1);
tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
/* If IPS we need to turn LED on. So we not
* not disable BIT 3/7 of reg3. */
@@ -1391,7 +1391,7 @@ static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
else
tmpu1b &= 0x73;
rtl_write_byte(rtlpriv, SYS_FUNC_EN + 1, tmpu1b);
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
/* wait for BIT 10/11/15 to pull high automatically!! */
mdelay(1);
@@ -1428,15 +1428,15 @@ static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
/* Set Digital Vdd to Retention isolation Path. */
tmpu2b = rtl_read_word(rtlpriv, SYS_ISO_CTRL);
rtl_write_word(rtlpriv, SYS_ISO_CTRL, (tmpu2b | BIT(11)));
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
/* For warm reboot NIC disappera bug. */
tmpu2b = rtl_read_word(rtlpriv, SYS_FUNC_EN);
rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(13)));
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
rtl_write_byte(rtlpriv, SYS_ISO_CTRL + 1, 0x68);
rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
/* Enable AFE PLL Macro Block */
tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
@@ -1447,17 +1447,17 @@ static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
mdelay(1);
/* Release isolation AFE PLL & MD */
rtl_write_byte(rtlpriv, SYS_ISO_CTRL, 0xA6);
rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
/* Enable MAC clock */
tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
/* Enable Core digital and enable IOREG R/W */
tmpu2b = rtl_read_word(rtlpriv, SYS_FUNC_EN);
rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(11)));
tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
/* enable REG_EN */
rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
/* Switch the control path. */
tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);