drm/sun4i: Reorganize UI layer code in DE2
Till now, DE2 driver supported only UI planes. Before we add support for VI planes, lets split out UI layer specific code from common parts. This commit does the following: - renames sun8i_layer.c to sun8i_ui_layer.c - moves UI channel specific code to sun8i_ui_layer.c - moves common code from sun8i_layer.c to sun8i_mixer.c - renames function and structure names so it is apparent where they belong to No functional change is made. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171201060550.10392-19-jernej.skrabec@siol.net
This commit is contained in:
Jernej Skrabec
@@ -26,14 +26,9 @@
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#include "sun4i_drv.h"
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#include "sun8i_mixer.h"
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#include "sun8i_layer.h"
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#include "sun8i_ui_layer.h"
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#include "sunxi_engine.h"
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struct de2_fmt_info {
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u32 drm_fmt;
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u32 de2_fmt;
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};
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static const struct de2_fmt_info de2_formats[] = {
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{
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.drm_fmt = DRM_FORMAT_ARGB8888,
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@@ -117,7 +112,7 @@ static const struct de2_fmt_info de2_formats[] = {
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},
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};
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static const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)
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const struct de2_fmt_info *sun8i_mixer_format_info(u32 format)
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{
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unsigned int i;
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@@ -136,157 +131,32 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine)
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SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
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}
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void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer, int channel,
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int overlay, bool enable)
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static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
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struct sunxi_engine *engine)
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{
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u32 val;
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struct drm_plane **planes;
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struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
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int i;
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DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n",
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enable ? "En" : "Dis", channel, overlay);
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planes = devm_kcalloc(drm->dev, mixer->cfg->ui_num + 1,
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sizeof(*planes), GFP_KERNEL);
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if (!planes)
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return ERR_PTR(-ENOMEM);
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if (enable)
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val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
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else
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val = 0;
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for (i = 0; i < mixer->cfg->ui_num; i++) {
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struct sun8i_ui_layer *layer;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(channel, overlay),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
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layer = sun8i_ui_layer_init_one(drm, mixer, i);
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if (IS_ERR(layer)) {
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dev_err(drm->dev, "Couldn't initialize %s plane\n",
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i ? "overlay" : "primary");
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return ERR_CAST(layer);
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};
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if (enable)
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val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(channel);
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else
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val = 0;
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planes[i] = &layer->plane;
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};
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_PIPE_CTL,
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SUN8I_MIXER_BLEND_PIPE_CTL_EN(channel), val);
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}
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int sun8i_mixer_update_layer_coord(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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u32 width, height, size;
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DRM_DEBUG_DRIVER("Updating channel %d overlay %d\n", channel, overlay);
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/*
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* Same source and destination width and height are guaranteed
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* by atomic check function.
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*/
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width = drm_rect_width(&state->dst);
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height = drm_rect_height(&state->dst);
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size = SUN8I_MIXER_SIZE(width, height);
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if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
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bool interlaced = false;
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u32 val;
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DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
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width, height);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_GLOBAL_SIZE,
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size);
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regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_OUTSIZE,
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size);
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if (state->crtc)
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interlaced = state->crtc->state->adjusted_mode.flags
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& DRM_MODE_FLAG_INTERLACE;
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if (interlaced)
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val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_OUTCTL,
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SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
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val);
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DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
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interlaced ? "on" : "off");
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}
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/* Set height and width */
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DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n", width, height);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_SIZE(channel, overlay),
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size);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_OVL_SIZE(channel),
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size);
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/* Set base coordinates */
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DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
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state->dst.x1, state->dst.y1);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_COORD(channel),
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SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_INSIZE(channel),
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size);
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return 0;
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}
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int sun8i_mixer_update_layer_formats(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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const struct de2_fmt_info *fmt_info;
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u32 val;
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fmt_info = sun8i_mixer_format_info(state->fb->format->format);
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if (!fmt_info) {
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DRM_DEBUG_DRIVER("Invalid format\n");
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return -EINVAL;
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}
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val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR(channel, overlay),
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SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
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return 0;
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}
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int sun8i_mixer_update_layer_buffer(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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struct drm_gem_cma_object *gem;
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dma_addr_t paddr;
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int bpp;
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/* Get the physical address of the buffer in memory */
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
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/* Compute the start of the displayed memory */
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bpp = fb->format->cpp[0];
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paddr = gem->paddr + fb->offsets[0];
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/* Fixup framebuffer address for src coordinates */
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paddr += (state->src.x1 >> 16) * bpp;
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paddr += (state->src.y1 >> 16) * fb->pitches[0];
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/* Set the line width */
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DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_PITCH(channel, overlay),
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fb->pitches[0]);
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DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(channel, overlay),
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lower_32_bits(paddr));
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return 0;
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return planes;
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}
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static const struct sunxi_engine_ops sun8i_engine_ops = {
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