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ARM: l2x0: Determine the cache size

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The cache size is needed for to optimise range based
maintainance operations

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
This commit is contained in:
Santosh Shilimkar
2010-07-11 14:35:37 +05:30
parent 7db27e864a
commit 5ba7037228
2 changed files with 12 additions and 2 deletions
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arch/arm/include/asm/hardware/cache-l2x0.h
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@@ -55,6 +55,7 @@
#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
#define L2X0_CACHE_ID_PART_L210 (1 << 6)
#define L2X0_CACHE_ID_PART_L310 (3 << 6)
#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17)
#ifndef __ASSEMBLY__
extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);