xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Browse Source 
Pull irq updates from Thomas Gleixner:
 "The usual pile of boring changes:

   - Consolidate tasklet functions to share code instead of duplicating
     it

   - The first step for making the low level entry handler management on
     multi-platform kernels generic

   - A new sysfs file which allows to retrieve the wakeup state of
     interrupts.

   - Ensure that the interrupt thread follows the effective affinity and
     not the programmed affinity to avoid cross core wakeups.

   - Two new interrupt controller drivers (Microsemi Ocelot and Qualcomm
     PDC)

   - Fix the wakeup path clock handling for Reneasas interrupt chips.

   - Rework the boot time register reset for ARM GIC-V2/3

   - Better suspend/resume support for ARM GIV-V3/ITS

   - Add missing locking to the ARM GIC set_type() callback

   - Small fixes for the irq simulator code

   - SPDX identifiers for the irq core code and removal of boiler plate

   - Small cleanups all over the place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits)
  openrisc: Set CONFIG_MULTI_IRQ_HANDLER
  arm64: Set CONFIG_MULTI_IRQ_HANDLER
  genirq: Make GENERIC_IRQ_MULTI_HANDLER depend on !MULTI_IRQ_HANDLER
  irqchip/gic: Take lock when updating irq type
  irqchip/gic: Update supports_deactivate static key to modern api
  irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling
  irqchip: Add a driver for the Microsemi Ocelot controller
  dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller
  irqchip/gic-v3: Probe for SCR_EL3 being clear before resetting AP0Rn
  irqchip/gic-v3: Don't try to reset AP0Rn
  irqchip/gic-v3: Do not check trigger configuration of partitionned LPIs
  genirq: Remove license boilerplate/references
  genirq: Add missing SPDX identifiers
  genirq/matrix: Cleanup SPDX identifier
  genirq: Cleanup top of file comments
  genirq: Pass desc to __irq_free instead of irq number
  irqchip/gic-v3: Loudly complain about the use of IRQ_TYPE_NONE
  irqchip/gic: Loudly complain about the use of IRQ_TYPE_NONE
  RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler
  genirq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER
  ...
This commit is contained in:
Linus Torvalds
2018-04-04 15:19:26 -07:00
parent 680014d6d1 83fbdf1c05
commit 5b1f3dc927
46 changed files with 1113 additions and 278 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/riscv/kernel/entry.S
View File

@@ -167,10 +167,9 @@ ENTRY(handle_exception)
bge s4, zero, 1f
/* Handle interrupts */
slli a0, s4, 1
srli a0, a0, 1
move a1, sp /* pt_regs */
tail do_IRQ
move a0, sp /* pt_regs */
REG_L a1, handle_arch_irq
jr a1
1:
/* Exceptions run with interrupts enabled */
csrs sstatus, SR_SIE

13
arch/riscv/kernel/irq.c
View File

@@ -24,16 +24,3 @@ void __init init_IRQ(void)
{
irqchip_init();
}
asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs)
{
#ifdef CONFIG_RISCV_INTC
/*
* FIXME: We don't want a direct call to riscv_intc_irq here. The plan
* is to put an IRQ domain here and let the interrupt controller
* register with that, but I poked around the arm64 code a bit and
* there might be a better way to do it (ie, something fully generic).
*/
riscv_intc_irq(cause, regs);
#endif
}