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[MIPS] Handle R4000/R4400 mfc0 from count register.

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The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.
This commit is contained in:
Ralf Baechle
2007-11-21 16:39:44 +00:00
parent 0f67e90e1c
commit 5aa85c9fc4
3 changed files with 43 additions and 61 deletions
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5
include/asm-mips/time.h
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@@ -58,11 +58,12 @@ extern int (*perf_irq)(void);
* Initialize the calling CPU's compare interrupt as clockevent device
*/
#ifdef CONFIG_CEVT_R4K
extern void mips_clockevent_init(void);
extern int mips_clockevent_init(void);
extern unsigned int __weak get_c0_compare_int(void);
#else
static inline void mips_clockevent_init(void)
static inline int mips_clockevent_init(void)
{
return -ENXIO;
}
#endif