Merge tag 'kvm-ppc-next-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc into HEAD
PPC KVM update for 5.2 * Support for guests to access the new POWER9 XIVE interrupt controller hardware directly, reducing interrupt latency and overhead for guests. * In-kernel implementation of the H_PAGE_INIT hypercall. * Reduce memory usage of sparsely-populated IOMMU tables. * Several bug fixes. Second PPC KVM update for 5.2 * Fix a bug, fix a spelling mistake, remove some useless code.
Cette révision appartient à :
Paolo Bonzini
@@ -1967,6 +1967,7 @@ registers, find a list below:
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PPC | KVM_REG_PPC_TLB3PS | 32
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PPC | KVM_REG_PPC_EPTCFG | 32
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PPC | KVM_REG_PPC_ICP_STATE | 64
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PPC | KVM_REG_PPC_VP_STATE | 128
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PPC | KVM_REG_PPC_TB_OFFSET | 64
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PPC | KVM_REG_PPC_SPMC1 | 32
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PPC | KVM_REG_PPC_SPMC2 | 32
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@@ -4487,6 +4488,15 @@ struct kvm_sync_regs {
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struct kvm_vcpu_events events;
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};
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6.75 KVM_CAP_PPC_IRQ_XIVE
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Architectures: ppc
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Target: vcpu
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Parameters: args[0] is the XIVE device fd
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args[1] is the XIVE CPU number (server ID) for this vcpu
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This capability connects the vcpu to an in-kernel XIVE device.
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7. Capabilities that can be enabled on VMs
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------------------------------------------
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197
Documentation/virtual/kvm/devices/xive.txt
Fichier normal
197
Documentation/virtual/kvm/devices/xive.txt
Fichier normal
@@ -0,0 +1,197 @@
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POWER9 eXternal Interrupt Virtualization Engine (XIVE Gen1)
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==========================================================
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Device types supported:
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KVM_DEV_TYPE_XIVE POWER9 XIVE Interrupt Controller generation 1
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This device acts as a VM interrupt controller. It provides the KVM
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interface to configure the interrupt sources of a VM in the underlying
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POWER9 XIVE interrupt controller.
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Only one XIVE instance may be instantiated. A guest XIVE device
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requires a POWER9 host and the guest OS should have support for the
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XIVE native exploitation interrupt mode. If not, it should run using
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the legacy interrupt mode, referred as XICS (POWER7/8).
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* Device Mappings
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The KVM device exposes different MMIO ranges of the XIVE HW which
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are required for interrupt management. These are exposed to the
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guest in VMAs populated with a custom VM fault handler.
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1. Thread Interrupt Management Area (TIMA)
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Each thread has an associated Thread Interrupt Management context
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composed of a set of registers. These registers let the thread
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handle priority management and interrupt acknowledgment. The most
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important are :
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- Interrupt Pending Buffer (IPB)
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- Current Processor Priority (CPPR)
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- Notification Source Register (NSR)
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They are exposed to software in four different pages each proposing
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a view with a different privilege. The first page is for the
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physical thread context and the second for the hypervisor. Only the
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third (operating system) and the fourth (user level) are exposed the
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guest.
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2. Event State Buffer (ESB)
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Each source is associated with an Event State Buffer (ESB) with
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either a pair of even/odd pair of pages which provides commands to
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manage the source: to trigger, to EOI, to turn off the source for
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instance.
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3. Device pass-through
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When a device is passed-through into the guest, the source
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interrupts are from a different HW controller (PHB4) and the ESB
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pages exposed to the guest should accommadate this change.
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The passthru_irq helpers, kvmppc_xive_set_mapped() and
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kvmppc_xive_clr_mapped() are called when the device HW irqs are
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mapped into or unmapped from the guest IRQ number space. The KVM
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device extends these helpers to clear the ESB pages of the guest IRQ
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number being mapped and then lets the VM fault handler repopulate.
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The handler will insert the ESB page corresponding to the HW
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interrupt of the device being passed-through or the initial IPI ESB
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page if the device has being removed.
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The ESB remapping is fully transparent to the guest and the OS
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device driver. All handling is done within VFIO and the above
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helpers in KVM-PPC.
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* Groups:
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1. KVM_DEV_XIVE_GRP_CTRL
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Provides global controls on the device
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Attributes:
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1.1 KVM_DEV_XIVE_RESET (write only)
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Resets the interrupt controller configuration for sources and event
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queues. To be used by kexec and kdump.
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Errors: none
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1.2 KVM_DEV_XIVE_EQ_SYNC (write only)
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Sync all the sources and queues and mark the EQ pages dirty. This
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to make sure that a consistent memory state is captured when
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migrating the VM.
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Errors: none
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2. KVM_DEV_XIVE_GRP_SOURCE (write only)
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Initializes a new source in the XIVE device and mask it.
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Attributes:
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Interrupt source number (64-bit)
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The kvm_device_attr.addr points to a __u64 value:
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bits: | 63 .... 2 | 1 | 0
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values: | unused | level | type
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- type: 0:MSI 1:LSI
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- level: assertion level in case of an LSI.
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Errors:
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-E2BIG: Interrupt source number is out of range
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-ENOMEM: Could not create a new source block
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-EFAULT: Invalid user pointer for attr->addr.
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-ENXIO: Could not allocate underlying HW interrupt
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3. KVM_DEV_XIVE_GRP_SOURCE_CONFIG (write only)
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Configures source targeting
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Attributes:
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Interrupt source number (64-bit)
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The kvm_device_attr.addr points to a __u64 value:
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bits: | 63 .... 33 | 32 | 31 .. 3 | 2 .. 0
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values: | eisn | mask | server | priority
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- priority: 0-7 interrupt priority level
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- server: CPU number chosen to handle the interrupt
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- mask: mask flag (unused)
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- eisn: Effective Interrupt Source Number
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Errors:
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-ENOENT: Unknown source number
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-EINVAL: Not initialized source number
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-EINVAL: Invalid priority
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-EINVAL: Invalid CPU number.
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-EFAULT: Invalid user pointer for attr->addr.
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-ENXIO: CPU event queues not configured or configuration of the
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underlying HW interrupt failed
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-EBUSY: No CPU available to serve interrupt
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4. KVM_DEV_XIVE_GRP_EQ_CONFIG (read-write)
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Configures an event queue of a CPU
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Attributes:
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EQ descriptor identifier (64-bit)
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The EQ descriptor identifier is a tuple (server, priority) :
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bits: | 63 .... 32 | 31 .. 3 | 2 .. 0
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values: | unused | server | priority
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The kvm_device_attr.addr points to :
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struct kvm_ppc_xive_eq {
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__u32 flags;
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__u32 qshift;
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__u64 qaddr;
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__u32 qtoggle;
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__u32 qindex;
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__u8 pad[40];
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};
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- flags: queue flags
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KVM_XIVE_EQ_ALWAYS_NOTIFY (required)
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forces notification without using the coalescing mechanism
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provided by the XIVE END ESBs.
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- qshift: queue size (power of 2)
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- qaddr: real address of queue
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- qtoggle: current queue toggle bit
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- qindex: current queue index
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- pad: reserved for future use
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Errors:
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-ENOENT: Invalid CPU number
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-EINVAL: Invalid priority
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-EINVAL: Invalid flags
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-EINVAL: Invalid queue size
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-EINVAL: Invalid queue address
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-EFAULT: Invalid user pointer for attr->addr.
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-EIO: Configuration of the underlying HW failed
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5. KVM_DEV_XIVE_GRP_SOURCE_SYNC (write only)
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Synchronize the source to flush event notifications
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Attributes:
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Interrupt source number (64-bit)
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Errors:
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-ENOENT: Unknown source number
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-EINVAL: Not initialized source number
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* VCPU state
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The XIVE IC maintains VP interrupt state in an internal structure
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called the NVT. When a VP is not dispatched on a HW processor
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thread, this structure can be updated by HW if the VP is the target
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of an event notification.
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It is important for migration to capture the cached IPB from the NVT
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as it synthesizes the priorities of the pending interrupts. We
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capture a bit more to report debug information.
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KVM_REG_PPC_VP_STATE (2 * 64bits)
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bits: | 63 .... 32 | 31 .... 0 |
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values: | TIMA word0 | TIMA word1 |
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bits: | 127 .......... 64 |
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values: | unused |
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* Migration:
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Saving the state of a VM using the XIVE native exploitation mode
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should follow a specific sequence. When the VM is stopped :
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1. Mask all sources (PQ=01) to stop the flow of events.
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2. Sync the XIVE device with the KVM control KVM_DEV_XIVE_EQ_SYNC to
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flush any in-flight event notification and to stabilize the EQs. At
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this stage, the EQ pages are marked dirty to make sure they are
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transferred in the migration sequence.
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3. Capture the state of the source targeting, the EQs configuration
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and the state of thread interrupt context registers.
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Restore is similar :
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1. Restore the EQ configuration. As targeting depends on it.
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2. Restore targeting
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3. Restore the thread interrupt contexts
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4. Restore the source states
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5. Let the vCPU run
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