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Merge branch 'omap3-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into omap-all

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This commit is contained in:
Russell King
2008-10-10 23:10:10 +01:00
committed by Russell King
parent 8e5bdc44ba 99b3075b90
commit 59aaade725
35 changed files with 5481 additions and 94 deletions
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9
arch/arm/plat-omap/Kconfig
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@@ -15,6 +15,9 @@ config ARCH_OMAP1
config ARCH_OMAP2
bool "TI OMAP2"
config ARCH_OMAP3
bool "TI OMAP3"
endchoice
comment "OMAP Feature Selections"
@@ -112,13 +115,13 @@ config OMAP_MPU_TIMER
config OMAP_32K_TIMER
bool "Use 32KHz timer"
depends on ARCH_OMAP16XX || ARCH_OMAP24XX
depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
help
Select this option if you want to enable the OMAP 32KHz timer.
This timer saves power compared to the OMAP_MPU_TIMER, and has
support for no tick during idle. The 32KHz timer provides less
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
currently only available for OMAP16XX and 24XX.
currently only available for OMAP16XX, 24XX and 34XX.
endchoice
@@ -133,7 +136,7 @@ config OMAP_32K_TIMER_HZ
config OMAP_DM_TIMER
bool "Use dual-mode timer"
depends on ARCH_OMAP16XX || ARCH_OMAP24XX
depends on ARCH_OMAP16XX || ARCH_OMAP24XX || ARCH_OMAP34XX
help
Select this option if you want to use OMAP Dual-Mode timers.

15
arch/arm/plat-omap/devices.c
View File

@@ -94,6 +94,10 @@ static inline void omap_init_dsp(void) { }
static void omap_init_kp(void)
{
/* 2430 and 34xx keypad is on TWL4030 */
if (cpu_is_omap2430() || cpu_is_omap34xx())
return;
if (machine_is_omap_h2() || machine_is_omap_h3()) {
omap_cfg_reg(F18_1610_KBC0);
omap_cfg_reg(D20_1610_KBC1);
@@ -395,8 +399,17 @@ static inline void omap_init_uwire(void) {}
#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP34XX)
#define OMAP_WDT_BASE 0x48314000
#elif defined(CONFIG_ARCH_OMAP24XX)
#ifdef CONFIG_ARCH_OMAP2430
/* WDT2 */
#define OMAP_WDT_BASE 0x49016000
#else
#define OMAP_WDT_BASE 0x48022000
#endif
#else
#define OMAP_WDT_BASE 0xfffeb000
#endif

36
arch/arm/plat-omap/include/mach/board-ldp.h Normal file
View File

@@ -0,0 +1,36 @@
/*
* arch/arm/plat-omap/include/mach/board-ldp.h
*
* Hardware definitions for TI OMAP3 LDP.
*
* Copyright (C) 2008 Texas Instruments Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP_LDP_H
#define __ASM_ARCH_OMAP_LDP_H
extern void twl4030_bci_battery_init(void);
#define TWL4030_IRQNUM INT_34XX_SYS_NIRQ
#endif /* __ASM_ARCH_OMAP_LDP_H */

33
arch/arm/plat-omap/include/mach/board-omap3beagle.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* arch/arm/plat-omap/include/mach/board-omap3beagle.h
*
* Hardware definitions for TI OMAP3 BEAGLE.
*
* Initial creation by Syed Mohammed Khasim <khasim@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OMAP3_BEAGLE_H
#define __ASM_ARCH_OMAP3_BEAGLE_H
#endif /* __ASM_ARCH_OMAP3_BEAGLE_H */

26
arch/arm/plat-omap/include/mach/board-overo.h Normal file
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@@ -0,0 +1,26 @@
/*
* board-overo.h (Gumstix Overo)
*
* Initial code: Steve Sakoman <steve@sakoman.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __ASM_ARCH_OVERO_H
#define __ASM_ARCH_OVERO_H
#define OVERO_GPIO_BT_XGATE 15
#define OVERO_GPIO_W2W_NRESET 16
#define OVERO_GPIO_BT_NRESET 164
#define OVERO_GPIO_USBH_CPEN 168
#define OVERO_GPIO_USBH_NRESET 183
#endif /* ____ASM_ARCH_OVERO_H */

12
arch/arm/plat-omap/include/mach/debug-macro.S
View File

@@ -35,6 +35,18 @@
#ifdef CONFIG_OMAP_LL_DEBUG_UART3
add \rx, \rx, #0x00004000 @ UART 3
#endif
#elif CONFIG_ARCH_OMAP3
moveq \rx, #0x48000000 @ physical base address
movne \rx, #0xd8000000 @ virtual base
orr \rx, \rx, #0x0006a000
#ifdef CONFIG_OMAP_LL_DEBUG_UART2
add \rx, \rx, #0x00002000 @ UART 2
#endif
#ifdef CONFIG_OMAP_LL_DEBUG_UART3
add \rx, \rx, #0x00fb0000 @ UART 3
add \rx, \rx, #0x00006000
#endif
#endif
.endm

12
arch/arm/plat-omap/include/mach/entry-macro.S
View File

@@ -55,9 +55,17 @@
1510:
.endm
#elif defined(CONFIG_ARCH_OMAP24XX)
#endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#if defined(CONFIG_ARCH_OMAP24XX)
#include <mach/omap24xx.h>
#endif
#if defined(CONFIG_ARCH_OMAP34XX)
#include <mach/omap34xx.h>
#endif
#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt number */
.macro disable_fiq
.endm
@@ -79,7 +87,7 @@
ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
cmp \irqnr, #0x0
2222:
ldrne \irqnr, [\base, #IRQ_SIR_IRQ]
ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
.endm

4
arch/arm/plat-omap/include/mach/gpmc.h
View File

@@ -84,6 +84,10 @@ struct gpmc_timings {
u16 access; /* Start-cycle to first data valid delay */
u16 rd_cycle; /* Total read cycle time */
u16 wr_cycle; /* Total write cycle time */
/* The following are only on OMAP3430 */
u16 wr_access; /* WRACCESSTIME */
u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */
};
extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);

8
arch/arm/plat-omap/include/mach/hardware.h
View File

@@ -322,6 +322,14 @@
#include "board-2430sdp.h"
#endif
#ifdef CONFIG_MACH_OMAP3_BEAGLE
#include "board-omap3beagle.h"
#endif
#ifdef CONFIG_MACH_OMAP_LDP
#include "board-ldp.h"
#endif
#ifdef CONFIG_MACH_OMAP_APOLLON
#include "board-apollon.h"
#endif

3
arch/arm/plat-omap/include/mach/io.h
View File

@@ -73,7 +73,6 @@
#define L4_24XX_VIRT 0xd8000000
#define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */
#ifdef CONFIG_ARCH_OMAP2430
#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */
#define L4_WK_243X_VIRT 0xd9000000
#define L4_WK_243X_SIZE SZ_1M
@@ -87,8 +86,6 @@
#define OMAP243X_SMS_VIRT 0xFC000000
#define OMAP243X_SMS_SIZE SZ_1M
#endif
#define IO_OFFSET 0x90000000
#define __IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
#define __OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */

35
arch/arm/plat-omap/include/mach/irqs.h
View File

@@ -286,6 +286,41 @@
#define INT_24XX_USB_IRQ_OTG 80
#define INT_24XX_MMC_IRQ 83
#define INT_34XX_BENCH_MPU_EMUL 3
#define INT_34XX_ST_MCBSP2_IRQ 4
#define INT_34XX_ST_MCBSP3_IRQ 5
#define INT_34XX_SSM_ABORT_IRQ 6
#define INT_34XX_SYS_NIRQ 7
#define INT_34XX_D2D_FW_IRQ 8
#define INT_34XX_PRCM_MPU_IRQ 11
#define INT_34XX_MCBSP1_IRQ 16
#define INT_34XX_MCBSP2_IRQ 17
#define INT_34XX_MCBSP3_IRQ 22
#define INT_34XX_MCBSP4_IRQ 23
#define INT_34XX_CAM_IRQ 24
#define INT_34XX_MCBSP5_IRQ 27
#define INT_34XX_GPIO_BANK1 29
#define INT_34XX_GPIO_BANK2 30
#define INT_34XX_GPIO_BANK3 31
#define INT_34XX_GPIO_BANK4 32
#define INT_34XX_GPIO_BANK5 33
#define INT_34XX_GPIO_BANK6 34
#define INT_34XX_USIM_IRQ 35
#define INT_34XX_WDT3_IRQ 36
#define INT_34XX_SPI4_IRQ 48
#define INT_34XX_SHA1MD52_IRQ 49
#define INT_34XX_FPKA_READY_IRQ 50
#define INT_34XX_SHA1MD51_IRQ 51
#define INT_34XX_RNG_IRQ 52
#define INT_34XX_I2C3_IRQ 61
#define INT_34XX_FPKA_ERROR_IRQ 64
#define INT_34XX_PBIAS_IRQ 75
#define INT_34XX_OHCI_IRQ 76
#define INT_34XX_EHCI_IRQ 77
#define INT_34XX_TLL_IRQ 78
#define INT_34XX_PARTHASH_IRQ 79
#define INT_34XX_MMC3_IRQ 94
#define INT_34XX_GPT12_IRQ 95
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
* 16 MPUIO lines */
#define OMAP_MAX_GPIO_LINES 192

2
arch/arm/plat-omap/include/mach/memory.h
View File

@@ -38,7 +38,7 @@
*/
#if defined(CONFIG_ARCH_OMAP1)
#define PHYS_OFFSET UL(0x10000000)
#elif defined(CONFIG_ARCH_OMAP2)
#elif defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
#define PHYS_OFFSET UL(0x80000000)
#endif

26
arch/arm/plat-omap/include/mach/mux.h
View File

@@ -723,7 +723,31 @@ enum omap34xx_index {
AB12_3430_USB3HS_TLL_DATA4,
AB13_3430_USB3HS_TLL_DATA5,
AA13_3430_USB3HS_TLL_DATA6,
AA12_3430_USB3HS_TLL_DATA7
AA12_3430_USB3HS_TLL_DATA7,
/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
AF10_3430_USB1FS_PHY_MM1_RXDP,
AG9_3430_USB1FS_PHY_MM1_RXDM,
W13_3430_USB1FS_PHY_MM1_RXRCV,
W12_3430_USB1FS_PHY_MM1_TXSE0,
W11_3430_USB1FS_PHY_MM1_TXDAT,
Y11_3430_USB1FS_PHY_MM1_TXEN_N,
/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
AF7_3430_USB2FS_PHY_MM2_RXDP,
AH7_3430_USB2FS_PHY_MM2_RXDM,
AB10_3430_USB2FS_PHY_MM2_RXRCV,
AB9_3430_USB2FS_PHY_MM2_TXSE0,
W3_3430_USB2FS_PHY_MM2_TXDAT,
T4_3430_USB2FS_PHY_MM2_TXEN_N,
/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
AH3_3430_USB3FS_PHY_MM3_RXDP,
AE3_3430_USB3FS_PHY_MM3_RXDM,
AD1_3430_USB3FS_PHY_MM3_RXRCV,
AE1_3430_USB3FS_PHY_MM3_TXSE0,
AD2_3430_USB3FS_PHY_MM3_TXDAT,
AC1_3430_USB3FS_PHY_MM3_TXEN_N,
};

1
arch/arm/plat-omap/include/mach/omap24xx.h
View File

@@ -39,7 +39,6 @@
/* interrupt controller */
#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
#define OMAP24XX_IVA_INTC_BASE 0x40000000
#define IRQ_SIR_IRQ 0x0040
#define OMAP2420_CTRL_BASE L4_24XX_BASE
#define OMAP2420_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)

4
arch/arm/plat-omap/include/mach/sdrc.h
View File

@@ -25,8 +25,8 @@
#define SDRC_DLLB_STATUS 0x06C
#define SDRC_POWER 0x070
#define SDRC_MR_0 0x084
#define SDRC_ACTIM_CTRL_A 0x09c
#define SDRC_ACTIM_CTRL_B 0x0a0
#define SDRC_ACTIM_CTRL_A_0 0x09c
#define SDRC_ACTIM_CTRL_B_0 0x0a0
#define SDRC_RFR_CTRL_0 0x0a4
/*

10
arch/arm/plat-omap/include/mach/sram.h
View File

@@ -21,6 +21,10 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2);
/* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
extern unsigned long omap1_sram_reprogram_clock_sz;
@@ -53,4 +57,10 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif

2
arch/arm/plat-omap/include/mach/system.h
View File

@@ -40,7 +40,7 @@ static inline void omap1_arch_reset(char mode)
static inline void arch_reset(char mode)
{
if (!cpu_is_omap24xx())
if (!cpu_class_is_omap2())
omap1_arch_reset(mode);
else
omap_prcm_arch_reset(mode);

32
arch/arm/plat-omap/io.c
View File

@@ -47,11 +47,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
}
#endif
#ifdef CONFIG_ARCH_OMAP2
if (cpu_class_is_omap2()) {
if (cpu_is_omap24xx()) {
if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE))
return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT);
if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE))
return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT);
}
if (cpu_is_omap2420()) {
if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE))
return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT);
if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE))
@@ -59,14 +61,36 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE))
return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT);
}
#ifdef CONFIG_ARCH_OMAP2430
if (cpu_is_omap2430()) {
if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE))
return XLATE(L4_WK_243X_PHYS, L4_WK_243X_VIRT);
return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT);
if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE))
return XLATE(OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT);
if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE))
return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT);
if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE))
return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT);
}
#endif
#ifdef CONFIG_ARCH_OMAP3
if (cpu_is_omap34xx()) {
if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE))
return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT);
if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE))
return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT);
if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE))
return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT);
if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE))
return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT);
if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE))
return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT);
if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE))
return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT);
if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE))
return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT);
if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE))
return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT);
}
#endif
return __arm_ioremap(p, size, type);

53
arch/arm/plat-omap/sram.c
View File

@@ -271,7 +271,7 @@ int __init omap1_sram_init(void)
#define omap1_sram_init() do {} while (0)
#endif
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
#if defined(CONFIG_ARCH_OMAP2)
static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
@@ -352,23 +352,19 @@ static inline int omap243x_sram_init(void)
#ifdef CONFIG_ARCH_OMAP3
static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
u32 omap2_sram_reprogram_gpmc(u32 perf_level)
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb,
u32 m2);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb, u32 m2)
{
if (!_omap2_sram_reprogram_gpmc)
if (!_omap3_sram_configure_core_dpll)
omap_sram_error();
return _omap2_sram_reprogram_gpmc(perf_level);
}
static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
u32 freqsel, u32 m2);
u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
{
if (!_omap2_sram_configure_core_dpll)
omap_sram_error();
return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla,
sdrc_actim_ctrlb, m2);
}
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
@@ -376,31 +372,16 @@ void restore_sram_functions(void)
{
omap_sram_ceil = omap_sram_base + omap_sram_size;
_omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
omap34xx_sram_reprogram_gpmc_sz);
_omap2_sram_configure_core_dpll =
omap_sram_push(omap34xx_sram_configure_core_dpll,
omap34xx_sram_configure_core_dpll_sz);
_omap3_sram_configure_core_dpll =
omap_sram_push(omap3_sram_configure_core_dpll,
omap3_sram_configure_core_dpll_sz);
}
int __init omap34xx_sram_init(void)
{
_omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
omap34xx_sram_ddr_init_sz);
_omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
omap34xx_sram_reprogram_sdrc_sz);
_omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
omap34xx_sram_set_prcm_sz);
_omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
omap34xx_sram_reprogram_gpmc_sz);
_omap2_sram_configure_core_dpll =
omap_sram_push(omap34xx_sram_configure_core_dpll,
omap34xx_sram_configure_core_dpll_sz);
_omap3_sram_configure_core_dpll =
omap_sram_push(omap3_sram_configure_core_dpll,
omap3_sram_configure_core_dpll_sz);
return 0;
}