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Blackfin arch: IO Port functions to read/write unalligned memory

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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich
2008-05-17 16:38:52 +08:00
committed by Bryan Wu
parent 86ad79321c
commit 5906967638
4 changed files with 37 additions and 4 deletions
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21
arch/blackfin/lib/ins.S
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@@ -7,7 +7,7 @@
* Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
* Copyright 2004-2008 Analog Devices Inc.
* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
@@ -63,6 +63,23 @@ ENTRY(_insw)
RTS;
ENDPROC(_insw)
ENTRY(_insw_8)
P0 = R0; /* P0 = port */
cli R3;
P1 = R1; /* P1 = address */
P2 = R2; /* P2 = count */
SSYNC;
LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
.Lword8_loop_s: R0 = W[P0];
B[P1++] = R0;
R0 = R0 >> 8;
B[P1++] = R0;
NOP;
.Lword8_loop_e: NOP;
sti R3;
RTS;
ENDPROC(_insw_8)
ENTRY(_insb)
P0 = R0; /* P0 = port */
cli R3;
@@ -78,8 +95,6 @@ ENTRY(_insb)
RTS;
ENDPROC(_insb)
ENTRY(_insl_16)
P0 = R0; /* P0 = port */
cli R3;