Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and 'clk-imx8mq' into clk-next
- NXP i.MX7ULP SoC clock support - Support for i.MX8QXP SoC clocks - Support for NXP i.MX8MQ clock controllers * clk-imx7ulp: clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support * clk-imx6-fixes: clk: imx6q: handle ENET PLL bypass clk: imx6q: optionally get CCM inputs via standard clock handles clk: imx6q: reset exclusive gates on init * clk-imx-fixes: clk: imx6q: add DCICx clocks gate clk: imx6sl: ensure MMDC CH0 handshake is bypassed clk: imx7d: remove UART1 clock setting * clk-imx8qxp: clk: imx: add imx8qxp lpcg driver clk: imx: add lpcg clock support clk: imx: add imx8qxp clk driver clk: imx: add scu clock common part clk: imx: add configuration option for mmio clks dt-bindings: clock: add imx8qxp lpcg clock binding dt-bindings: clock: imx8qxp: add SCU clock IDs firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile * clk-imx8mq: clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant clk: imx: remove redundant initialization of ret to zero clk: imx: Add SCCG PLL type clk: imx: Add fractional PLL output clock clk: imx: Add clock driver for i.MX8MQ CCM clk: imx: Add imx composite clock dt-bindings: Add binding for i.MX8MQ CCM
This commit is contained in:
Stephen Boyd
@@ -274,6 +274,8 @@
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#define IMX6QDL_CLK_EPIT1 261
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#define IMX6QDL_CLK_EPIT2 262
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#define IMX6QDL_CLK_MMDC_P0_IPG 263
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#define IMX6QDL_CLK_END 264
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#define IMX6QDL_CLK_DCIC1 264
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#define IMX6QDL_CLK_DCIC2 265
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#define IMX6QDL_CLK_END 266
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#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
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109
include/dt-bindings/clock/imx7ulp-clock.h
Normal file
109
include/dt-bindings/clock/imx7ulp-clock.h
Normal file
@@ -0,0 +1,109 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017~2018 NXP
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
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#define __DT_BINDINGS_CLOCK_IMX7ULP_H
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/* SCG1 */
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#define IMX7ULP_CLK_DUMMY 0
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#define IMX7ULP_CLK_ROSC 1
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#define IMX7ULP_CLK_SOSC 2
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#define IMX7ULP_CLK_FIRC 3
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#define IMX7ULP_CLK_SPLL_PRE_SEL 4
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#define IMX7ULP_CLK_SPLL_PRE_DIV 5
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#define IMX7ULP_CLK_SPLL 6
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#define IMX7ULP_CLK_SPLL_POST_DIV1 7
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#define IMX7ULP_CLK_SPLL_POST_DIV2 8
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#define IMX7ULP_CLK_SPLL_PFD0 9
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#define IMX7ULP_CLK_SPLL_PFD1 10
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#define IMX7ULP_CLK_SPLL_PFD2 11
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#define IMX7ULP_CLK_SPLL_PFD3 12
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#define IMX7ULP_CLK_SPLL_PFD_SEL 13
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#define IMX7ULP_CLK_SPLL_SEL 14
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#define IMX7ULP_CLK_APLL_PRE_SEL 15
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#define IMX7ULP_CLK_APLL_PRE_DIV 16
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#define IMX7ULP_CLK_APLL 17
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#define IMX7ULP_CLK_APLL_POST_DIV1 18
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#define IMX7ULP_CLK_APLL_POST_DIV2 19
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#define IMX7ULP_CLK_APLL_PFD0 20
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#define IMX7ULP_CLK_APLL_PFD1 21
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#define IMX7ULP_CLK_APLL_PFD2 22
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#define IMX7ULP_CLK_APLL_PFD3 23
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#define IMX7ULP_CLK_APLL_PFD_SEL 24
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#define IMX7ULP_CLK_APLL_SEL 25
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#define IMX7ULP_CLK_UPLL 26
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#define IMX7ULP_CLK_SYS_SEL 27
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#define IMX7ULP_CLK_CORE_DIV 28
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#define IMX7ULP_CLK_BUS_DIV 29
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#define IMX7ULP_CLK_PLAT_DIV 30
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#define IMX7ULP_CLK_DDR_SEL 31
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#define IMX7ULP_CLK_DDR_DIV 32
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#define IMX7ULP_CLK_NIC_SEL 33
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#define IMX7ULP_CLK_NIC0_DIV 34
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#define IMX7ULP_CLK_GPU_DIV 35
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#define IMX7ULP_CLK_NIC1_DIV 36
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#define IMX7ULP_CLK_NIC1_BUS_DIV 37
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#define IMX7ULP_CLK_NIC1_EXT_DIV 38
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#define IMX7ULP_CLK_MIPI_PLL 39
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#define IMX7ULP_CLK_SIRC 40
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#define IMX7ULP_CLK_SOSC_BUS_CLK 41
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#define IMX7ULP_CLK_FIRC_BUS_CLK 42
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#define IMX7ULP_CLK_SPLL_BUS_CLK 43
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#define IMX7ULP_CLK_SCG1_END 44
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/* PCC2 */
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#define IMX7ULP_CLK_DMA1 0
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#define IMX7ULP_CLK_RGPIO2P1 1
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#define IMX7ULP_CLK_FLEXBUS 2
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#define IMX7ULP_CLK_SEMA42_1 3
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#define IMX7ULP_CLK_DMA_MUX1 4
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#define IMX7ULP_CLK_SNVS 5
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#define IMX7ULP_CLK_CAAM 6
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#define IMX7ULP_CLK_LPTPM4 7
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#define IMX7ULP_CLK_LPTPM5 8
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#define IMX7ULP_CLK_LPIT1 9
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#define IMX7ULP_CLK_LPSPI2 10
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#define IMX7ULP_CLK_LPSPI3 11
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#define IMX7ULP_CLK_LPI2C4 12
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#define IMX7ULP_CLK_LPI2C5 13
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#define IMX7ULP_CLK_LPUART4 14
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#define IMX7ULP_CLK_LPUART5 15
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#define IMX7ULP_CLK_FLEXIO1 16
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#define IMX7ULP_CLK_USB0 17
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#define IMX7ULP_CLK_USB1 18
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#define IMX7ULP_CLK_USB_PHY 19
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#define IMX7ULP_CLK_USB_PL301 20
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#define IMX7ULP_CLK_USDHC0 21
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#define IMX7ULP_CLK_USDHC1 22
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#define IMX7ULP_CLK_WDG1 23
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#define IMX7ULP_CLK_WDG2 24
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#define IMX7ULP_CLK_PCC2_END 25
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/* PCC3 */
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#define IMX7ULP_CLK_LPTPM6 0
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#define IMX7ULP_CLK_LPTPM7 1
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#define IMX7ULP_CLK_LPI2C6 2
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#define IMX7ULP_CLK_LPI2C7 3
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#define IMX7ULP_CLK_LPUART6 4
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#define IMX7ULP_CLK_LPUART7 5
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#define IMX7ULP_CLK_VIU 6
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#define IMX7ULP_CLK_DSI 7
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#define IMX7ULP_CLK_LCDIF 8
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#define IMX7ULP_CLK_MMDC 9
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#define IMX7ULP_CLK_PCTLC 10
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#define IMX7ULP_CLK_PCTLD 11
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#define IMX7ULP_CLK_PCTLE 12
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#define IMX7ULP_CLK_PCTLF 13
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#define IMX7ULP_CLK_GPU3D 14
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#define IMX7ULP_CLK_GPU2D 15
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#define IMX7ULP_CLK_PCC3_END 16
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#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
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395
include/dt-bindings/clock/imx8mq-clock.h
Normal file
395
include/dt-bindings/clock/imx8mq-clock.h
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@@ -0,0 +1,395 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
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#define __DT_BINDINGS_CLOCK_IMX8MQ_H
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#define IMX8MQ_CLK_DUMMY 0
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#define IMX8MQ_CLK_32K 1
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#define IMX8MQ_CLK_25M 2
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#define IMX8MQ_CLK_27M 3
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#define IMX8MQ_CLK_EXT1 4
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#define IMX8MQ_CLK_EXT2 5
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#define IMX8MQ_CLK_EXT3 6
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#define IMX8MQ_CLK_EXT4 7
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/* ANAMIX PLL clocks */
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/* FRAC PLLs */
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/* ARM PLL */
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#define IMX8MQ_ARM_PLL_REF_SEL 8
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#define IMX8MQ_ARM_PLL_REF_DIV 9
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#define IMX8MQ_ARM_PLL 10
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#define IMX8MQ_ARM_PLL_BYPASS 11
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#define IMX8MQ_ARM_PLL_OUT 12
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/* GPU PLL */
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#define IMX8MQ_GPU_PLL_REF_SEL 13
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#define IMX8MQ_GPU_PLL_REF_DIV 14
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#define IMX8MQ_GPU_PLL 15
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#define IMX8MQ_GPU_PLL_BYPASS 16
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#define IMX8MQ_GPU_PLL_OUT 17
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/* VPU PLL */
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#define IMX8MQ_VPU_PLL_REF_SEL 18
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#define IMX8MQ_VPU_PLL_REF_DIV 19
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#define IMX8MQ_VPU_PLL 20
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#define IMX8MQ_VPU_PLL_BYPASS 21
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#define IMX8MQ_VPU_PLL_OUT 22
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/* AUDIO PLL1 */
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#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
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#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
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#define IMX8MQ_AUDIO_PLL1 25
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#define IMX8MQ_AUDIO_PLL1_BYPASS 26
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#define IMX8MQ_AUDIO_PLL1_OUT 27
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/* AUDIO PLL2 */
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#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
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#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
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#define IMX8MQ_AUDIO_PLL2 30
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#define IMX8MQ_AUDIO_PLL2_BYPASS 31
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#define IMX8MQ_AUDIO_PLL2_OUT 32
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/* VIDEO PLL1 */
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#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
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#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
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#define IMX8MQ_VIDEO_PLL1 35
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#define IMX8MQ_VIDEO_PLL1_BYPASS 36
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#define IMX8MQ_VIDEO_PLL1_OUT 37
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/* SYS1 PLL */
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#define IMX8MQ_SYS1_PLL1_REF_SEL 38
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#define IMX8MQ_SYS1_PLL1_REF_DIV 39
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#define IMX8MQ_SYS1_PLL1 40
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#define IMX8MQ_SYS1_PLL1_OUT 41
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#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
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#define IMX8MQ_SYS1_PLL2 43
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#define IMX8MQ_SYS1_PLL2_DIV 44
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#define IMX8MQ_SYS1_PLL2_OUT 45
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/* SYS2 PLL */
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#define IMX8MQ_SYS2_PLL1_REF_SEL 46
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#define IMX8MQ_SYS2_PLL1_REF_DIV 47
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#define IMX8MQ_SYS2_PLL1 48
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#define IMX8MQ_SYS2_PLL1_OUT 49
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#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
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#define IMX8MQ_SYS2_PLL2 51
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#define IMX8MQ_SYS2_PLL2_DIV 52
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#define IMX8MQ_SYS2_PLL2_OUT 53
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/* SYS3 PLL */
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#define IMX8MQ_SYS3_PLL1_REF_SEL 54
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#define IMX8MQ_SYS3_PLL1_REF_DIV 55
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#define IMX8MQ_SYS3_PLL1 56
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#define IMX8MQ_SYS3_PLL1_OUT 57
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#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
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#define IMX8MQ_SYS3_PLL2 59
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#define IMX8MQ_SYS3_PLL2_DIV 60
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#define IMX8MQ_SYS3_PLL2_OUT 61
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/* DRAM PLL */
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#define IMX8MQ_DRAM_PLL1_REF_SEL 62
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#define IMX8MQ_DRAM_PLL1_REF_DIV 63
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#define IMX8MQ_DRAM_PLL1 64
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#define IMX8MQ_DRAM_PLL1_OUT 65
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#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
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#define IMX8MQ_DRAM_PLL2 67
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#define IMX8MQ_DRAM_PLL2_DIV 68
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#define IMX8MQ_DRAM_PLL2_OUT 69
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/* SYS PLL DIV */
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#define IMX8MQ_SYS1_PLL_40M 70
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#define IMX8MQ_SYS1_PLL_80M 71
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#define IMX8MQ_SYS1_PLL_100M 72
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#define IMX8MQ_SYS1_PLL_133M 73
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#define IMX8MQ_SYS1_PLL_160M 74
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#define IMX8MQ_SYS1_PLL_200M 75
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#define IMX8MQ_SYS1_PLL_266M 76
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#define IMX8MQ_SYS1_PLL_400M 77
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#define IMX8MQ_SYS1_PLL_800M 78
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#define IMX8MQ_SYS2_PLL_50M 79
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#define IMX8MQ_SYS2_PLL_100M 80
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#define IMX8MQ_SYS2_PLL_125M 81
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#define IMX8MQ_SYS2_PLL_166M 82
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#define IMX8MQ_SYS2_PLL_200M 83
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#define IMX8MQ_SYS2_PLL_250M 84
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#define IMX8MQ_SYS2_PLL_333M 85
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#define IMX8MQ_SYS2_PLL_500M 86
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#define IMX8MQ_SYS2_PLL_1000M 87
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/* CCM ROOT clocks */
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/* A53 */
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#define IMX8MQ_CLK_A53_SRC 88
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#define IMX8MQ_CLK_A53_CG 89
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#define IMX8MQ_CLK_A53_DIV 90
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/* M4 */
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#define IMX8MQ_CLK_M4_SRC 91
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#define IMX8MQ_CLK_M4_CG 92
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#define IMX8MQ_CLK_M4_DIV 93
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/* VPU */
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#define IMX8MQ_CLK_VPU_SRC 94
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#define IMX8MQ_CLK_VPU_CG 95
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#define IMX8MQ_CLK_VPU_DIV 96
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/* GPU CORE */
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#define IMX8MQ_CLK_GPU_CORE_SRC 97
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#define IMX8MQ_CLK_GPU_CORE_CG 98
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#define IMX8MQ_CLK_GPU_CORE_DIV 99
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/* GPU SHADER */
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#define IMX8MQ_CLK_GPU_SHADER_SRC 100
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#define IMX8MQ_CLK_GPU_SHADER_CG 101
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#define IMX8MQ_CLK_GPU_SHADER_DIV 102
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/* BUS TYPE */
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/* MAIN AXI */
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#define IMX8MQ_CLK_MAIN_AXI 103
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/* ENET AXI */
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#define IMX8MQ_CLK_ENET_AXI 104
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/* NAND_USDHC_BUS */
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#define IMX8MQ_CLK_NAND_USDHC_BUS 105
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/* VPU BUS */
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#define IMX8MQ_CLK_VPU_BUS 106
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/* DISP_AXI */
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#define IMX8MQ_CLK_DISP_AXI 107
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/* DISP APB */
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#define IMX8MQ_CLK_DISP_APB 108
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/* DISP RTRM */
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#define IMX8MQ_CLK_DISP_RTRM 109
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/* USB_BUS */
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#define IMX8MQ_CLK_USB_BUS 110
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/* GPU_AXI */
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#define IMX8MQ_CLK_GPU_AXI 111
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/* GPU_AHB */
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#define IMX8MQ_CLK_GPU_AHB 112
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/* NOC */
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#define IMX8MQ_CLK_NOC 113
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/* NOC_APB */
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#define IMX8MQ_CLK_NOC_APB 115
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/* AHB */
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#define IMX8MQ_CLK_AHB 116
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/* AUDIO AHB */
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#define IMX8MQ_CLK_AUDIO_AHB 117
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/* DRAM_ALT */
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#define IMX8MQ_CLK_DRAM_ALT 118
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/* DRAM APB */
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#define IMX8MQ_CLK_DRAM_APB 119
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/* VPU_G1 */
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#define IMX8MQ_CLK_VPU_G1 120
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/* VPU_G2 */
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#define IMX8MQ_CLK_VPU_G2 121
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/* DISP_DTRC */
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#define IMX8MQ_CLK_DISP_DTRC 122
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/* DISP_DC8000 */
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#define IMX8MQ_CLK_DISP_DC8000 123
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/* PCIE_CTRL */
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#define IMX8MQ_CLK_PCIE1_CTRL 124
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/* PCIE_PHY */
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#define IMX8MQ_CLK_PCIE1_PHY 125
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/* PCIE_AUX */
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#define IMX8MQ_CLK_PCIE1_AUX 126
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/* DC_PIXEL */
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#define IMX8MQ_CLK_DC_PIXEL 127
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/* LCDIF_PIXEL */
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#define IMX8MQ_CLK_LCDIF_PIXEL 128
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/* SAI1~6 */
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#define IMX8MQ_CLK_SAI1 129
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#define IMX8MQ_CLK_SAI2 130
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#define IMX8MQ_CLK_SAI3 131
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#define IMX8MQ_CLK_SAI4 132
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#define IMX8MQ_CLK_SAI5 133
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#define IMX8MQ_CLK_SAI6 134
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/* SPDIF1 */
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#define IMX8MQ_CLK_SPDIF1 135
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/* SPDIF2 */
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#define IMX8MQ_CLK_SPDIF2 136
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/* ENET_REF */
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#define IMX8MQ_CLK_ENET_REF 137
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/* ENET_TIMER */
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#define IMX8MQ_CLK_ENET_TIMER 138
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/* ENET_PHY */
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#define IMX8MQ_CLK_ENET_PHY_REF 139
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/* NAND */
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#define IMX8MQ_CLK_NAND 140
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/* QSPI */
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#define IMX8MQ_CLK_QSPI 141
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/* USDHC1 */
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#define IMX8MQ_CLK_USDHC1 142
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/* USDHC2 */
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#define IMX8MQ_CLK_USDHC2 143
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/* I2C1 */
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#define IMX8MQ_CLK_I2C1 144
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/* I2C2 */
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#define IMX8MQ_CLK_I2C2 145
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/* I2C3 */
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#define IMX8MQ_CLK_I2C3 146
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/* I2C4 */
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#define IMX8MQ_CLK_I2C4 147
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/* UART1 */
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#define IMX8MQ_CLK_UART1 148
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/* UART2 */
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#define IMX8MQ_CLK_UART2 149
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/* UART3 */
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#define IMX8MQ_CLK_UART3 150
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/* UART4 */
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#define IMX8MQ_CLK_UART4 151
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/* USB_CORE_REF */
|
||||
#define IMX8MQ_CLK_USB_CORE_REF 152
|
||||
/* USB_PHY_REF */
|
||||
#define IMX8MQ_CLK_USB_PHY_REF 163
|
||||
/* ECSPI1 */
|
||||
#define IMX8MQ_CLK_ECSPI1 164
|
||||
/* ECSPI2 */
|
||||
#define IMX8MQ_CLK_ECSPI2 165
|
||||
/* PWM1 */
|
||||
#define IMX8MQ_CLK_PWM1 166
|
||||
/* PWM2 */
|
||||
#define IMX8MQ_CLK_PWM2 167
|
||||
/* PWM3 */
|
||||
#define IMX8MQ_CLK_PWM3 168
|
||||
/* PWM4 */
|
||||
#define IMX8MQ_CLK_PWM4 169
|
||||
/* GPT1 */
|
||||
#define IMX8MQ_CLK_GPT1 170
|
||||
/* WDOG */
|
||||
#define IMX8MQ_CLK_WDOG 171
|
||||
/* WRCLK */
|
||||
#define IMX8MQ_CLK_WRCLK 172
|
||||
/* DSI_CORE */
|
||||
#define IMX8MQ_CLK_DSI_CORE 173
|
||||
/* DSI_PHY */
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF 174
|
||||
/* DSI_DBI */
|
||||
#define IMX8MQ_CLK_DSI_DBI 175
|
||||
/*DSI_ESC */
|
||||
#define IMX8MQ_CLK_DSI_ESC 176
|
||||
/* CSI1_CORE */
|
||||
#define IMX8MQ_CLK_CSI1_CORE 177
|
||||
/* CSI1_PHY */
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF 178
|
||||
/* CSI_ESC */
|
||||
#define IMX8MQ_CLK_CSI1_ESC 179
|
||||
/* CSI2_CORE */
|
||||
#define IMX8MQ_CLK_CSI2_CORE 170
|
||||
/* CSI2_PHY */
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF 181
|
||||
/* CSI2_ESC */
|
||||
#define IMX8MQ_CLK_CSI2_ESC 182
|
||||
/* PCIE2_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL 183
|
||||
/* PCIE2_PHY */
|
||||
#define IMX8MQ_CLK_PCIE2_PHY 184
|
||||
/* PCIE2_AUX */
|
||||
#define IMX8MQ_CLK_PCIE2_AUX 185
|
||||
/* ECSPI3 */
|
||||
#define IMX8MQ_CLK_ECSPI3 186
|
||||
|
||||
/* CCGR clocks */
|
||||
#define IMX8MQ_CLK_A53_ROOT 187
|
||||
#define IMX8MQ_CLK_DRAM_ROOT 188
|
||||
#define IMX8MQ_CLK_ECSPI1_ROOT 189
|
||||
#define IMX8MQ_CLK_ECSPI2_ROOT 180
|
||||
#define IMX8MQ_CLK_ECSPI3_ROOT 181
|
||||
#define IMX8MQ_CLK_ENET1_ROOT 182
|
||||
#define IMX8MQ_CLK_GPT1_ROOT 193
|
||||
#define IMX8MQ_CLK_I2C1_ROOT 194
|
||||
#define IMX8MQ_CLK_I2C2_ROOT 195
|
||||
#define IMX8MQ_CLK_I2C3_ROOT 196
|
||||
#define IMX8MQ_CLK_I2C4_ROOT 197
|
||||
#define IMX8MQ_CLK_M4_ROOT 198
|
||||
#define IMX8MQ_CLK_PCIE1_ROOT 199
|
||||
#define IMX8MQ_CLK_PCIE2_ROOT 200
|
||||
#define IMX8MQ_CLK_PWM1_ROOT 201
|
||||
#define IMX8MQ_CLK_PWM2_ROOT 202
|
||||
#define IMX8MQ_CLK_PWM3_ROOT 203
|
||||
#define IMX8MQ_CLK_PWM4_ROOT 204
|
||||
#define IMX8MQ_CLK_QSPI_ROOT 205
|
||||
#define IMX8MQ_CLK_SAI1_ROOT 206
|
||||
#define IMX8MQ_CLK_SAI2_ROOT 207
|
||||
#define IMX8MQ_CLK_SAI3_ROOT 208
|
||||
#define IMX8MQ_CLK_SAI4_ROOT 209
|
||||
#define IMX8MQ_CLK_SAI5_ROOT 210
|
||||
#define IMX8MQ_CLK_SAI6_ROOT 212
|
||||
#define IMX8MQ_CLK_UART1_ROOT 213
|
||||
#define IMX8MQ_CLK_UART2_ROOT 214
|
||||
#define IMX8MQ_CLK_UART3_ROOT 215
|
||||
#define IMX8MQ_CLK_UART4_ROOT 216
|
||||
#define IMX8MQ_CLK_USB1_CTRL_ROOT 217
|
||||
#define IMX8MQ_CLK_USB2_CTRL_ROOT 218
|
||||
#define IMX8MQ_CLK_USB1_PHY_ROOT 219
|
||||
#define IMX8MQ_CLK_USB2_PHY_ROOT 220
|
||||
#define IMX8MQ_CLK_USDHC1_ROOT 221
|
||||
#define IMX8MQ_CLK_USDHC2_ROOT 222
|
||||
#define IMX8MQ_CLK_WDOG1_ROOT 223
|
||||
#define IMX8MQ_CLK_WDOG2_ROOT 224
|
||||
#define IMX8MQ_CLK_WDOG3_ROOT 225
|
||||
#define IMX8MQ_CLK_GPU_ROOT 226
|
||||
#define IMX8MQ_CLK_HEVC_ROOT 227
|
||||
#define IMX8MQ_CLK_AVC_ROOT 228
|
||||
#define IMX8MQ_CLK_VP9_ROOT 229
|
||||
#define IMX8MQ_CLK_HEVC_INTER_ROOT 230
|
||||
#define IMX8MQ_CLK_DISP_ROOT 231
|
||||
#define IMX8MQ_CLK_HDMI_ROOT 232
|
||||
#define IMX8MQ_CLK_HDMI_PHY_ROOT 233
|
||||
#define IMX8MQ_CLK_VPU_DEC_ROOT 234
|
||||
#define IMX8MQ_CLK_CSI1_ROOT 235
|
||||
#define IMX8MQ_CLK_CSI2_ROOT 236
|
||||
#define IMX8MQ_CLK_RAWNAND_ROOT 237
|
||||
#define IMX8MQ_CLK_SDMA1_ROOT 238
|
||||
#define IMX8MQ_CLK_SDMA2_ROOT 239
|
||||
#define IMX8MQ_CLK_VPU_G1_ROOT 240
|
||||
#define IMX8MQ_CLK_VPU_G2_ROOT 241
|
||||
|
||||
/* SCCG PLL GATE */
|
||||
#define IMX8MQ_SYS1_PLL_OUT 232
|
||||
#define IMX8MQ_SYS2_PLL_OUT 243
|
||||
#define IMX8MQ_SYS3_PLL_OUT 244
|
||||
#define IMX8MQ_DRAM_PLL_OUT 245
|
||||
|
||||
#define IMX8MQ_GPT_3M_CLK 246
|
||||
|
||||
#define IMX8MQ_CLK_IPG_ROOT 247
|
||||
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 248
|
||||
#define IMX8MQ_CLK_SAI1_IPG 249
|
||||
#define IMX8MQ_CLK_SAI2_IPG 250
|
||||
#define IMX8MQ_CLK_SAI3_IPG 251
|
||||
#define IMX8MQ_CLK_SAI4_IPG 252
|
||||
#define IMX8MQ_CLK_SAI5_IPG 253
|
||||
#define IMX8MQ_CLK_SAI6_IPG 254
|
||||
|
||||
/* DSI AHB/IPG clocks */
|
||||
/* rxesc clock */
|
||||
#define IMX8MQ_CLK_DSI_AHB 255
|
||||
/* txesc clock */
|
||||
#define IMX8MQ_CLK_DSI_IPG_DIV 256
|
||||
|
||||
#define IMX8MQ_CLK_TMU_ROOT 265
|
||||
|
||||
/* Display root clocks */
|
||||
#define IMX8MQ_CLK_DISP_AXI_ROOT 266
|
||||
#define IMX8MQ_CLK_DISP_APB_ROOT 267
|
||||
#define IMX8MQ_CLK_DISP_RTRM_ROOT 268
|
||||
|
||||
#define IMX8MQ_CLK_OCOTP_ROOT 269
|
||||
|
||||
#define IMX8MQ_CLK_DRAM_ALT_ROOT 270
|
||||
#define IMX8MQ_CLK_DRAM_CORE 271
|
||||
|
||||
#define IMX8MQ_CLK_MU_ROOT 272
|
||||
#define IMX8MQ_VIDEO2_PLL_OUT 273
|
||||
|
||||
#define IMX8MQ_CLK_CLKO2 274
|
||||
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 275
|
||||
|
||||
#define IMX8MQ_CLK_END 276
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
289
include/dt-bindings/clock/imx8qxp-clock.h
Normal file
289
include/dt-bindings/clock/imx8qxp-clock.h
Normal file
@@ -0,0 +1,289 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
* Dong Aisheng <aisheng.dong@nxp.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8QXP_H
|
||||
|
||||
/* SCU Clocks */
|
||||
|
||||
#define IMX8QXP_CLK_DUMMY 0
|
||||
|
||||
/* CPU */
|
||||
#define IMX8QXP_A35_CLK 1
|
||||
|
||||
/* LSIO SS */
|
||||
#define IMX8QXP_LSIO_MEM_CLK 2
|
||||
#define IMX8QXP_LSIO_BUS_CLK 3
|
||||
#define IMX8QXP_LSIO_PWM0_CLK 10
|
||||
#define IMX8QXP_LSIO_PWM1_CLK 11
|
||||
#define IMX8QXP_LSIO_PWM2_CLK 12
|
||||
#define IMX8QXP_LSIO_PWM3_CLK 13
|
||||
#define IMX8QXP_LSIO_PWM4_CLK 14
|
||||
#define IMX8QXP_LSIO_PWM5_CLK 15
|
||||
#define IMX8QXP_LSIO_PWM6_CLK 16
|
||||
#define IMX8QXP_LSIO_PWM7_CLK 17
|
||||
#define IMX8QXP_LSIO_GPT0_CLK 18
|
||||
#define IMX8QXP_LSIO_GPT1_CLK 19
|
||||
#define IMX8QXP_LSIO_GPT2_CLK 20
|
||||
#define IMX8QXP_LSIO_GPT3_CLK 21
|
||||
#define IMX8QXP_LSIO_GPT4_CLK 22
|
||||
#define IMX8QXP_LSIO_FSPI0_CLK 23
|
||||
#define IMX8QXP_LSIO_FSPI1_CLK 24
|
||||
|
||||
/* Connectivity SS */
|
||||
#define IMX8QXP_CONN_AXI_CLK_ROOT 30
|
||||
#define IMX8QXP_CONN_AHB_CLK_ROOT 31
|
||||
#define IMX8QXP_CONN_IPG_CLK_ROOT 32
|
||||
#define IMX8QXP_CONN_SDHC0_CLK 40
|
||||
#define IMX8QXP_CONN_SDHC1_CLK 41
|
||||
#define IMX8QXP_CONN_SDHC2_CLK 42
|
||||
#define IMX8QXP_CONN_ENET0_ROOT_CLK 43
|
||||
#define IMX8QXP_CONN_ENET0_BYPASS_CLK 44
|
||||
#define IMX8QXP_CONN_ENET0_RGMII_CLK 45
|
||||
#define IMX8QXP_CONN_ENET1_ROOT_CLK 46
|
||||
#define IMX8QXP_CONN_ENET1_BYPASS_CLK 47
|
||||
#define IMX8QXP_CONN_ENET1_RGMII_CLK 48
|
||||
#define IMX8QXP_CONN_GPMI_BCH_IO_CLK 49
|
||||
#define IMX8QXP_CONN_GPMI_BCH_CLK 50
|
||||
#define IMX8QXP_CONN_USB2_ACLK 51
|
||||
#define IMX8QXP_CONN_USB2_BUS_CLK 52
|
||||
#define IMX8QXP_CONN_USB2_LPM_CLK 53
|
||||
|
||||
/* HSIO SS */
|
||||
#define IMX8QXP_HSIO_AXI_CLK 60
|
||||
#define IMX8QXP_HSIO_PER_CLK 61
|
||||
|
||||
/* Display controller SS */
|
||||
#define IMX8QXP_DC_AXI_EXT_CLK 70
|
||||
#define IMX8QXP_DC_AXI_INT_CLK 71
|
||||
#define IMX8QXP_DC_CFG_CLK 72
|
||||
#define IMX8QXP_DC0_PLL0_CLK 80
|
||||
#define IMX8QXP_DC0_PLL1_CLK 81
|
||||
#define IMX8QXP_DC0_DISP0_CLK 82
|
||||
#define IMX8QXP_DC0_DISP1_CLK 83
|
||||
|
||||
/* MIPI-LVDS SS */
|
||||
#define IMX8QXP_MIPI_IPG_CLK 90
|
||||
#define IMX8QXP_MIPI0_PIXEL_CLK 100
|
||||
#define IMX8QXP_MIPI0_BYPASS_CLK 101
|
||||
#define IMX8QXP_MIPI0_LVDS_PIXEL_CLK 102
|
||||
#define IMX8QXP_MIPI0_LVDS_BYPASS_CLK 103
|
||||
#define IMX8QXP_MIPI0_LVDS_PHY_CLK 104
|
||||
#define IMX8QXP_MIPI0_I2C0_CLK 105
|
||||
#define IMX8QXP_MIPI0_I2C1_CLK 106
|
||||
#define IMX8QXP_MIPI0_PWM0_CLK 107
|
||||
#define IMX8QXP_MIPI1_PIXEL_CLK 108
|
||||
#define IMX8QXP_MIPI1_BYPASS_CLK 109
|
||||
#define IMX8QXP_MIPI1_LVDS_PIXEL_CLK 110
|
||||
#define IMX8QXP_MIPI1_LVDS_BYPASS_CLK 111
|
||||
#define IMX8QXP_MIPI1_LVDS_PHY_CLK 112
|
||||
#define IMX8QXP_MIPI1_I2C0_CLK 113
|
||||
#define IMX8QXP_MIPI1_I2C1_CLK 114
|
||||
#define IMX8QXP_MIPI1_PWM0_CLK 115
|
||||
|
||||
/* IMG SS */
|
||||
#define IMX8QXP_IMG_AXI_CLK 120
|
||||
#define IMX8QXP_IMG_IPG_CLK 121
|
||||
#define IMX8QXP_IMG_PXL_CLK 122
|
||||
|
||||
/* MIPI-CSI SS */
|
||||
#define IMX8QXP_CSI0_CORE_CLK 130
|
||||
#define IMX8QXP_CSI0_ESC_CLK 131
|
||||
#define IMX8QXP_CSI0_PWM0_CLK 132
|
||||
#define IMX8QXP_CSI0_I2C0_CLK 133
|
||||
|
||||
/* PARALLER CSI SS */
|
||||
#define IMX8QXP_PARALLEL_CSI_DPLL_CLK 140
|
||||
#define IMX8QXP_PARALLEL_CSI_PIXEL_CLK 141
|
||||
#define IMX8QXP_PARALLEL_CSI_MCLK_CLK 142
|
||||
|
||||
/* VPU SS */
|
||||
#define IMX8QXP_VPU_ENC_CLK 150
|
||||
#define IMX8QXP_VPU_DEC_CLK 151
|
||||
|
||||
/* GPU SS */
|
||||
#define IMX8QXP_GPU0_CORE_CLK 160
|
||||
#define IMX8QXP_GPU0_SHADER_CLK 161
|
||||
|
||||
/* ADMA SS */
|
||||
#define IMX8QXP_ADMA_IPG_CLK_ROOT 165
|
||||
#define IMX8QXP_ADMA_UART0_CLK 170
|
||||
#define IMX8QXP_ADMA_UART1_CLK 171
|
||||
#define IMX8QXP_ADMA_UART2_CLK 172
|
||||
#define IMX8QXP_ADMA_UART3_CLK 173
|
||||
#define IMX8QXP_ADMA_SPI0_CLK 174
|
||||
#define IMX8QXP_ADMA_SPI1_CLK 175
|
||||
#define IMX8QXP_ADMA_SPI2_CLK 176
|
||||
#define IMX8QXP_ADMA_SPI3_CLK 177
|
||||
#define IMX8QXP_ADMA_CAN0_CLK 178
|
||||
#define IMX8QXP_ADMA_CAN1_CLK 179
|
||||
#define IMX8QXP_ADMA_CAN2_CLK 180
|
||||
#define IMX8QXP_ADMA_I2C0_CLK 181
|
||||
#define IMX8QXP_ADMA_I2C1_CLK 182
|
||||
#define IMX8QXP_ADMA_I2C2_CLK 183
|
||||
#define IMX8QXP_ADMA_I2C3_CLK 184
|
||||
#define IMX8QXP_ADMA_FTM0_CLK 185
|
||||
#define IMX8QXP_ADMA_FTM1_CLK 186
|
||||
#define IMX8QXP_ADMA_ADC0_CLK 187
|
||||
#define IMX8QXP_ADMA_PWM_CLK 188
|
||||
#define IMX8QXP_ADMA_LCD_CLK 189
|
||||
|
||||
#define IMX8QXP_SCU_CLK_END 190
|
||||
|
||||
/* LPCG clocks */
|
||||
|
||||
/* LSIO SS LPCG */
|
||||
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_CLK 0
|
||||
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_S_CLK 1
|
||||
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_HF_CLK 2
|
||||
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
|
||||
#define IMX8QXP_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
|
||||
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_CLK 5
|
||||
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_S_CLK 6
|
||||
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_HF_CLK 7
|
||||
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
|
||||
#define IMX8QXP_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
|
||||
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_CLK 10
|
||||
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_S_CLK 11
|
||||
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_HF_CLK 12
|
||||
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
|
||||
#define IMX8QXP_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
|
||||
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_CLK 15
|
||||
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_S_CLK 16
|
||||
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_HF_CLK 17
|
||||
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
|
||||
#define IMX8QXP_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
|
||||
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_CLK 20
|
||||
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_S_CLK 21
|
||||
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_HF_CLK 22
|
||||
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
|
||||
#define IMX8QXP_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
|
||||
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_CLK 25
|
||||
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_S_CLK 26
|
||||
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_HF_CLK 27
|
||||
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
|
||||
#define IMX8QXP_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
|
||||
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_CLK 30
|
||||
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_S_CLK 31
|
||||
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_HF_CLK 32
|
||||
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
|
||||
#define IMX8QXP_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
|
||||
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_CLK 35
|
||||
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_S_CLK 36
|
||||
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_HF_CLK 37
|
||||
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
|
||||
#define IMX8QXP_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
|
||||
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_CLK 40
|
||||
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_S_CLK 41
|
||||
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_HF_CLK 42
|
||||
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
|
||||
#define IMX8QXP_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
|
||||
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_CLK 45
|
||||
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_S_CLK 46
|
||||
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_HF_CLK 47
|
||||
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
|
||||
#define IMX8QXP_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
|
||||
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_CLK 50
|
||||
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_S_CLK 51
|
||||
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_HF_CLK 52
|
||||
#define IMX8QXP_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
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#define IMX8QXP_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
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#define IMX8QXP_LSIO_LPCG_GPT3_IPG_CLK 55
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#define IMX8QXP_LSIO_LPCG_GPT3_IPG_S_CLK 56
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#define IMX8QXP_LSIO_LPCG_GPT3_IPG_HF_CLK 57
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#define IMX8QXP_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
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#define IMX8QXP_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
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#define IMX8QXP_LSIO_LPCG_GPT4_IPG_CLK 60
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#define IMX8QXP_LSIO_LPCG_GPT4_IPG_S_CLK 61
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#define IMX8QXP_LSIO_LPCG_GPT4_IPG_HF_CLK 62
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#define IMX8QXP_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
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#define IMX8QXP_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
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#define IMX8QXP_LSIO_LPCG_FSPI0_HCLK 65
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#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_CLK 66
|
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#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_S_CLK 67
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#define IMX8QXP_LSIO_LPCG_FSPI0_IPG_SFCK 68
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#define IMX8QXP_LSIO_LPCG_FSPI1_HCLK 69
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#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_CLK 70
|
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#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_S_CLK 71
|
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#define IMX8QXP_LSIO_LPCG_FSPI1_IPG_SFCK 72
|
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|
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#define IMX8QXP_LSIO_LPCG_CLK_END 73
|
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|
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/* Connectivity SS LPCG */
|
||||
#define IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK 0
|
||||
#define IMX8QXP_CONN_LPCG_SDHC0_PER_CLK 1
|
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#define IMX8QXP_CONN_LPCG_SDHC0_HCLK 2
|
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#define IMX8QXP_CONN_LPCG_SDHC1_IPG_CLK 3
|
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#define IMX8QXP_CONN_LPCG_SDHC1_PER_CLK 4
|
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#define IMX8QXP_CONN_LPCG_SDHC1_HCLK 5
|
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#define IMX8QXP_CONN_LPCG_SDHC2_IPG_CLK 6
|
||||
#define IMX8QXP_CONN_LPCG_SDHC2_PER_CLK 7
|
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#define IMX8QXP_CONN_LPCG_SDHC2_HCLK 8
|
||||
#define IMX8QXP_CONN_LPCG_GPMI_APB_CLK 9
|
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#define IMX8QXP_CONN_LPCG_GPMI_BCH_APB_CLK 10
|
||||
#define IMX8QXP_CONN_LPCG_GPMI_BCH_IO_CLK 11
|
||||
#define IMX8QXP_CONN_LPCG_GPMI_BCH_CLK 12
|
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#define IMX8QXP_CONN_LPCG_APBHDMA_CLK 13
|
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#define IMX8QXP_CONN_LPCG_ENET0_ROOT_CLK 14
|
||||
#define IMX8QXP_CONN_LPCG_ENET0_TX_CLK 15
|
||||
#define IMX8QXP_CONN_LPCG_ENET0_AHB_CLK 16
|
||||
#define IMX8QXP_CONN_LPCG_ENET0_IPG_S_CLK 17
|
||||
#define IMX8QXP_CONN_LPCG_ENET0_IPG_CLK 18
|
||||
|
||||
#define IMX8QXP_CONN_LPCG_ENET1_ROOT_CLK 19
|
||||
#define IMX8QXP_CONN_LPCG_ENET1_TX_CLK 20
|
||||
#define IMX8QXP_CONN_LPCG_ENET1_AHB_CLK 21
|
||||
#define IMX8QXP_CONN_LPCG_ENET1_IPG_S_CLK 22
|
||||
#define IMX8QXP_CONN_LPCG_ENET1_IPG_CLK 23
|
||||
|
||||
#define IMX8QXP_CONN_LPCG_CLK_END 24
|
||||
|
||||
/* ADMA SS LPCG */
|
||||
#define IMX8QXP_ADMA_LPCG_UART0_IPG_CLK 0
|
||||
#define IMX8QXP_ADMA_LPCG_UART0_BAUD_CLK 1
|
||||
#define IMX8QXP_ADMA_LPCG_UART1_IPG_CLK 2
|
||||
#define IMX8QXP_ADMA_LPCG_UART1_BAUD_CLK 3
|
||||
#define IMX8QXP_ADMA_LPCG_UART2_IPG_CLK 4
|
||||
#define IMX8QXP_ADMA_LPCG_UART2_BAUD_CLK 5
|
||||
#define IMX8QXP_ADMA_LPCG_UART3_IPG_CLK 6
|
||||
#define IMX8QXP_ADMA_LPCG_UART3_BAUD_CLK 7
|
||||
#define IMX8QXP_ADMA_LPCG_SPI0_IPG_CLK 8
|
||||
#define IMX8QXP_ADMA_LPCG_SPI1_IPG_CLK 9
|
||||
#define IMX8QXP_ADMA_LPCG_SPI2_IPG_CLK 10
|
||||
#define IMX8QXP_ADMA_LPCG_SPI3_IPG_CLK 11
|
||||
#define IMX8QXP_ADMA_LPCG_SPI0_CLK 12
|
||||
#define IMX8QXP_ADMA_LPCG_SPI1_CLK 13
|
||||
#define IMX8QXP_ADMA_LPCG_SPI2_CLK 14
|
||||
#define IMX8QXP_ADMA_LPCG_SPI3_CLK 15
|
||||
#define IMX8QXP_ADMA_LPCG_CAN0_IPG_CLK 16
|
||||
#define IMX8QXP_ADMA_LPCG_CAN0_IPG_PE_CLK 17
|
||||
#define IMX8QXP_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
|
||||
#define IMX8QXP_ADMA_LPCG_CAN1_IPG_CLK 19
|
||||
#define IMX8QXP_ADMA_LPCG_CAN1_IPG_PE_CLK 20
|
||||
#define IMX8QXP_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
|
||||
#define IMX8QXP_ADMA_LPCG_CAN2_IPG_CLK 22
|
||||
#define IMX8QXP_ADMA_LPCG_CAN2_IPG_PE_CLK 23
|
||||
#define IMX8QXP_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
|
||||
#define IMX8QXP_ADMA_LPCG_I2C0_CLK 25
|
||||
#define IMX8QXP_ADMA_LPCG_I2C1_CLK 26
|
||||
#define IMX8QXP_ADMA_LPCG_I2C2_CLK 27
|
||||
#define IMX8QXP_ADMA_LPCG_I2C3_CLK 28
|
||||
#define IMX8QXP_ADMA_LPCG_I2C0_IPG_CLK 29
|
||||
#define IMX8QXP_ADMA_LPCG_I2C1_IPG_CLK 30
|
||||
#define IMX8QXP_ADMA_LPCG_I2C2_IPG_CLK 31
|
||||
#define IMX8QXP_ADMA_LPCG_I2C3_IPG_CLK 32
|
||||
#define IMX8QXP_ADMA_LPCG_FTM0_CLK 33
|
||||
#define IMX8QXP_ADMA_LPCG_FTM1_CLK 34
|
||||
#define IMX8QXP_ADMA_LPCG_FTM0_IPG_CLK 35
|
||||
#define IMX8QXP_ADMA_LPCG_FTM1_IPG_CLK 36
|
||||
#define IMX8QXP_ADMA_LPCG_PWM_HI_CLK 37
|
||||
#define IMX8QXP_ADMA_LPCG_PWM_IPG_CLK 38
|
||||
#define IMX8QXP_ADMA_LPCG_LCD_PIX_CLK 39
|
||||
#define IMX8QXP_ADMA_LPCG_LCD_APB_CLK 40
|
||||
|
||||
#define IMX8QXP_ADMA_LPCG_CLK_END 41
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
|
||||
Reference in New Issue
Block a user