Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and 'clk-imx8mq' into clk-next
- NXP i.MX7ULP SoC clock support - Support for i.MX8QXP SoC clocks - Support for NXP i.MX8MQ clock controllers * clk-imx7ulp: clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support * clk-imx6-fixes: clk: imx6q: handle ENET PLL bypass clk: imx6q: optionally get CCM inputs via standard clock handles clk: imx6q: reset exclusive gates on init * clk-imx-fixes: clk: imx6q: add DCICx clocks gate clk: imx6sl: ensure MMDC CH0 handshake is bypassed clk: imx7d: remove UART1 clock setting * clk-imx8qxp: clk: imx: add imx8qxp lpcg driver clk: imx: add lpcg clock support clk: imx: add imx8qxp clk driver clk: imx: add scu clock common part clk: imx: add configuration option for mmio clks dt-bindings: clock: add imx8qxp lpcg clock binding dt-bindings: clock: imx8qxp: add SCU clock IDs firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile * clk-imx8mq: clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant clk: imx: remove redundant initialization of ret to zero clk: imx: Add SCCG PLL type clk: imx: Add fractional PLL output clock clk: imx: Add clock driver for i.MX8MQ CCM clk: imx: Add imx composite clock dt-bindings: Add binding for i.MX8MQ CCM
This commit is contained in:
Stephen Boyd
@@ -8,6 +8,7 @@
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extern spinlock_t imx_ccm_lock;
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void imx_check_clocks(struct clk *clks[], unsigned int count);
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void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
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void imx_register_uart_clocks(struct clk ** const clks[]);
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extern void imx_cscmr1_fixup(u32 *val);
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@@ -21,12 +22,24 @@ enum imx_pllv1_type {
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IMX_PLLV1_IMX35,
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};
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enum imx_sccg_pll_type {
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SCCG_PLL1,
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SCCG_PLL2,
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};
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struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
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const char *parent, void __iomem *base);
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struct clk *imx_clk_pllv2(const char *name, const char *parent,
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void __iomem *base);
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struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,
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void __iomem *base);
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struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name,
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void __iomem *base,
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enum imx_sccg_pll_type pll_type);
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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@@ -42,6 +55,9 @@ enum imx_pllv3_type {
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent_name, void __iomem *base, u32 div_mask);
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struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
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void __iomem *base);
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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@@ -51,26 +67,38 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
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struct clk * imx_obtain_fixed_clock(
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const char *name, unsigned long rate);
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struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
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const char *name);
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struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u32 exclusive_mask);
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struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx);
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struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
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void __iomem *reg, u8 idx);
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struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
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void __iomem *reg, u8 shift, u8 width,
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void __iomem *busy_reg, u8 busy_shift);
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struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
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u8 width, void __iomem *busy_reg, u8 busy_shift,
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const char **parent_names, int num_parents);
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const char * const *parent_names, int num_parents);
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struct clk_hw *imx7ulp_clk_composite(const char *name,
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const char * const *parent_names,
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int num_parents, bool mux_present,
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bool rate_present, bool gate_present,
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void __iomem *reg);
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struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width,
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void (*fixup)(u32 *val));
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struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents,
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u8 shift, u8 width, const char * const *parents,
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int num_parents, void (*fixup)(u32 *val));
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static inline struct clk *imx_clk_fixed(const char *name, int rate)
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@@ -78,8 +106,19 @@ static inline struct clk *imx_clk_fixed(const char *name, int rate)
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return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
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}
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static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
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{
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return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
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}
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static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate)
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{
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return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
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}
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static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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u8 shift, u8 width, const char * const *parents,
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int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
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@@ -100,6 +139,15 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_clk_hw_divider(const char *name,
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const char *parent,
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void __iomem *reg, u8 shift,
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u8 width)
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{
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return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_divider_flags(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 width,
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unsigned long flags)
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@@ -108,6 +156,15 @@ static inline struct clk *imx_clk_divider_flags(const char *name,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
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const char *parent,
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void __iomem *reg, u8 shift,
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u8 width, unsigned long flags)
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{
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return clk_hw_register_divider(NULL, name, parent, flags,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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@@ -116,6 +173,15 @@ static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_divider2_flags(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 width,
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unsigned long flags)
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{
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return clk_register_divider(NULL, name, parent,
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flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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@@ -130,6 +196,13 @@ static inline struct clk *imx_clk_gate_flags(const char *name, const char *paren
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shift, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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@@ -190,6 +263,15 @@ static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
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reg, shift, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate3_flags(const char *name,
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const char *parent, void __iomem *reg, u8 shift,
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unsigned long flags)
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{
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return clk_register_gate(NULL, name, parent,
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flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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@@ -198,8 +280,18 @@ static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
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reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_gate4_flags(const char *name,
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const char *parent, void __iomem *reg, u8 shift,
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unsigned long flags)
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{
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return clk_register_gate2(NULL, name, parent,
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flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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u8 shift, u8 width, const char * const *parents,
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int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT, reg, shift,
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@@ -207,24 +299,78 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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}
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static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, int num_parents)
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u8 shift, u8 width, const char * const *parents,
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int num_parents)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
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u8 shift, u8 width,
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const char * const *parents,
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int num_parents)
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{
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return clk_hw_register_mux(NULL, name, parents, num_parents,
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CLK_SET_RATE_NO_REPARENT |
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CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux_flags(const char *name,
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void __iomem *reg, u8 shift, u8 width, const char **parents,
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int num_parents, unsigned long flags)
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void __iomem *reg, u8 shift, u8 width,
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const char * const *parents, int num_parents,
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unsigned long flags)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
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&imx_ccm_lock);
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}
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static inline struct clk *imx_clk_mux2_flags(const char *name,
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void __iomem *reg, u8 shift, u8 width, const char **parents,
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int num_parents, unsigned long flags)
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{
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return clk_register_mux(NULL, name, parents, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
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void __iomem *reg, u8 shift,
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u8 width,
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const char * const *parents,
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int num_parents,
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unsigned long flags)
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{
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return clk_hw_register_mux(NULL, name, parents, num_parents,
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flags | CLK_SET_RATE_NO_REPARENT,
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reg, shift, width, 0, &imx_ccm_lock);
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}
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struct clk *imx_clk_cpu(const char *name, const char *parent_name,
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struct clk *div, struct clk *mux, struct clk *pll,
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struct clk *step);
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struct clk *imx8m_clk_composite_flags(const char *name,
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const char **parent_names,
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int num_parents, void __iomem *reg,
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unsigned long flags);
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#define __imx8m_clk_composite(name, parent_names, reg, flags) \
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imx8m_clk_composite_flags(name, parent_names, \
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ARRAY_SIZE(parent_names), reg, \
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flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
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#define imx8m_clk_composite(name, parent_names, reg) \
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__imx8m_clk_composite(name, parent_names, reg, 0)
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#define imx8m_clk_composite_critical(name, parent_names, reg) \
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__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
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struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, const struct clk_div_table *table,
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spinlock_t *lock);
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#endif
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