Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', 'clk-imx8qxp' and 'clk-imx8mq' into clk-next
- NXP i.MX7ULP SoC clock support - Support for i.MX8QXP SoC clocks - Support for NXP i.MX8MQ clock controllers * clk-imx7ulp: clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support * clk-imx6-fixes: clk: imx6q: handle ENET PLL bypass clk: imx6q: optionally get CCM inputs via standard clock handles clk: imx6q: reset exclusive gates on init * clk-imx-fixes: clk: imx6q: add DCICx clocks gate clk: imx6sl: ensure MMDC CH0 handshake is bypassed clk: imx7d: remove UART1 clock setting * clk-imx8qxp: clk: imx: add imx8qxp lpcg driver clk: imx: add lpcg clock support clk: imx: add imx8qxp clk driver clk: imx: add scu clock common part clk: imx: add configuration option for mmio clks dt-bindings: clock: add imx8qxp lpcg clock binding dt-bindings: clock: imx8qxp: add SCU clock IDs firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile * clk-imx8mq: clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant clk: imx: remove redundant initialization of ret to zero clk: imx: Add SCCG PLL type clk: imx: Add fractional PLL output clock clk: imx: Add clock driver for i.MX8MQ CCM clk: imx: Add imx composite clock dt-bindings: Add binding for i.MX8MQ CCM
这个提交包含在：
Stephen Boyd
@@ -225,6 +225,41 @@ static void of_assigned_ldb_sels(struct device_node *node,
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}
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}
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static bool pll6_bypassed(struct device_node *node)
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{
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int index, ret, num_clocks;
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struct of_phandle_args clkspec;
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num_clocks = of_count_phandle_with_args(node, "assigned-clocks",
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"#clock-cells");
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if (num_clocks < 0)
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return false;
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for (index = 0; index < num_clocks; index++) {
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ret = of_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", index,
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&clkspec);
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if (ret < 0)
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return false;
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if (clkspec.np == node &&
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clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
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break;
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}
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/* PLL6 bypass is not part of the assigned clock list */
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if (index == num_clocks)
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return false;
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ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
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"#clock-cells", index, &clkspec);
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if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
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return true;
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return false;
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}
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#define CCM_CCDR 0x04
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#define CCM_CCSR 0x0c
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#define CCM_CS2CDR 0x2c
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@@ -414,12 +449,24 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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int ret;
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clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
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clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
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clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
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clk[IMX6QDL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
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if (IS_ERR(clk[IMX6QDL_CLK_CKIL]))
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clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
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clk[IMX6QDL_CLK_CKIH] = of_clk_get_by_name(ccm_node, "ckih1");
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if (IS_ERR(clk[IMX6QDL_CLK_CKIH]))
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clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
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clk[IMX6QDL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
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if (IS_ERR(clk[IMX6QDL_CLK_OSC]))
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clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
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/* Clock source from external clock via CLK1/2 PADs */
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clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
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clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
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clk[IMX6QDL_CLK_ANACLK1] = of_clk_get_by_name(ccm_node, "anaclk1");
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if (IS_ERR(clk[IMX6QDL_CLK_ANACLK1]))
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clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
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clk[IMX6QDL_CLK_ANACLK2] = of_clk_get_by_name(ccm_node, "anaclk2");
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if (IS_ERR(clk[IMX6QDL_CLK_ANACLK2]))
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clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
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anatop_base = base = of_iomap(np, 0);
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@@ -491,16 +538,32 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
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clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
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clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
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clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
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/*
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* The ENET PLL is special in that is has multiple outputs with
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* different post-dividers that are all affected by the single bypass
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* bit, so a single mux bit affects 3 independent branches of the clock
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* tree. There is no good way to model this in the clock framework and
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* dynamically changing the bypass bit, will yield unexpected results.
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* So we treat any configuration that bypasses the ENET PLL as
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* essentially static with the divider ratios reflecting the bypass
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* status.
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*
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*/
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if (!pll6_bypassed(ccm_node)) {
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clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
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clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
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clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
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base + 0xe0, 0, 2, 0, clk_enet_ref_table,
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&imx_ccm_lock);
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} else {
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clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 1);
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clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 1);
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clk[IMX6QDL_CLK_ENET_REF] = imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1);
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}
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clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
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clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
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clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
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base + 0xe0, 0, 2, 0, clk_enet_ref_table,
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&imx_ccm_lock);
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clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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@@ -508,8 +571,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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* lvds1_gate and lvds2_gate are pseudo-gates. Both can be
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* independently configured as clock inputs or outputs. We treat
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* the "output_enable" bit as a gate, even though it's really just
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* enabling clock output.
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* enabling clock output. Initially the gate bits are cleared, as
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* otherwise the exclusive configuration gets locked in the setup done
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* by software running before the clock driver, with no way to change
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* it.
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*/
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writel(readl(base + 0x160) & ~0x3c00, base + 0x160);
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clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
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clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
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@@ -737,6 +804,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
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clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
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clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
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clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
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clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
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clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
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clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
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clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
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