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MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions

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Use the regular tlb_do_page_fault_0 (no write) handler to handle
the RI and XI exceptions. Also skip the RI/XI validation check
on TLB load handler since it's redundant when the CPU has
unique RI/XI exceptions.

Singed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7339/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Leonid Yegoshin
2014-07-15 14:09:56 +01:00
committed by Ralf Baechle
parent 6ee729aa6c
commit 5890f70f15
2 changed files with 9 additions and 2 deletions
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4
arch/mips/mm/tlbex.c
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@@ -1919,7 +1919,7 @@ static void build_r4000_tlb_load_handler(void)
if (m4kc_tlbp_war())
build_tlb_probe_entry(&p);
if (cpu_has_rixi) {
if (cpu_has_rixi && !cpu_has_rixiex) {
/*
* If the page is not _PAGE_VALID, RI or XI could not
* have triggered it. Skip the expensive test..
@@ -1986,7 +1986,7 @@ static void build_r4000_tlb_load_handler(void)
build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
build_tlb_probe_entry(&p);
if (cpu_has_rixi) {
if (cpu_has_rixi && !cpu_has_rixiex) {
/*
* If the page is not _PAGE_VALID, RI or XI could not
* have triggered it. Skip the expensive test..