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Merge tag 'mfd-3.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6

Browse Source 
Pull MFD changes from Samuel Ortiz:
 "MFD bits for the 3.7 merge window.

  As usual we have a few new drivers:

   - TI LP8788
   - TI OMAP USB TLL
   - Maxim MAX8907
   - SMSC ECE1099
   - Dialog Semiconductor DA9055
   - A simpler syscon driver that allow us to get rid of the anatop one.

  Drivers are also gradually getting Device Tree and IRQ domain support.

  The following drivers got DT support:
   - palmas, 88pm860x, tc3589x and twl4030-audio

  And those ones now use the IRQ domain APIs:
   - 88pm860x, tc3589x, db8500_prcmu

  Also some other interesting changes:
   - Intel's ICH LPC now supports Lynx Point
   - TI's twl4030-audio added a GPO child
   - tps6527 enabled its backlight subdevice
   - The twl6030 pwm driver moved to the new PWM subsystem

  And finally a bunch of cleanup and casual fixes for mc13xxx, 88pm860x,
  palmas, ab8500, wm8994, wm5110, max8907 and the tps65xxx family."

Fix up various annoying conflicts: the DT and IRQ domain support came in
twice and was already in 3.6. And then it was apparently rebased.

Guys, DON'T REBASE!

* tag 'mfd-3.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (89 commits)
  ARM: dts: Enable 88pm860x pmic
  mfd: 88pm860x: Move gpadc init into touch
  mfd: 88pm860x: Device tree support
  mfd: 88pm860x: Use irqdomain
  mfd: smsc: Add support for smsc gpio io/keypad driver
  backlight: tps65217_bl: Add missing platform_set_drvdata in tps65217_bl_probe
  mfd: DA9055 core driver
  mfd: tps65910: Add alarm interrupt of TPS65910 RTC to mfd device list
  mfd: wm5110: Add register patches for revision B
  mfd: wm5110: Disable control interface error report for WM5110 rev B
  mfd: max8907: Remove regulator-compatible from DT docs
  backlight: Add TPS65217 WLED driver
  mfd: Add backlight as subdevice to the tps65217
  mfd: Provide the PRCMU with its own IRQ domain
  mfd: Fix max8907 sparse warning
  mfd: Add lp8788 mfd driver
  mfd: dbx500: Provide a more accurate smp_twd clock
  mfd: rc5t583: Fix warning messages
  regulator: palmas: Add DT support
  mfd: palmas: Change regulator defns to better suite DT
  ...
This commit is contained in:
Linus Torvalds
2012-10-05 12:01:30 +09:00
parent ecefbd94b8 74d8378159
commit 578f1ef91a
105 changed files with 7893 additions and 1808 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
include/linux/mfd/88pm860x.h
View File

@@ -34,22 +34,6 @@ enum {
PM8606_ID_MAX,
};
enum {
PM8606_BACKLIGHT1 = 0,
PM8606_BACKLIGHT2,
PM8606_BACKLIGHT3,
};
enum {
PM8606_LED1_RED = 0,
PM8606_LED1_GREEN,
PM8606_LED1_BLUE,
PM8606_LED2_RED,
PM8606_LED2_GREEN,
PM8606_LED2_BLUE,
PM8607_LED_VIBRATOR,
};
/* 8606 Registers */
#define PM8606_DCM_BOOST (0x00)
@@ -322,7 +306,7 @@ struct pm860x_chip {
struct regmap *regmap_companion;
int buck3_double; /* DVC ramp slope double */
unsigned short companion_addr;
int companion_addr;
unsigned short osc_vote;
int id;
int irq_mode;
@@ -340,16 +324,12 @@ enum {
};
struct pm860x_backlight_pdata {
int id;
int pwm;
int iset;
unsigned long flags;
};
struct pm860x_led_pdata {
int id;
int iset;
unsigned long flags;
};
struct pm860x_rtc_pdata {
@@ -379,15 +359,29 @@ struct pm860x_platform_data {
struct pm860x_rtc_pdata *rtc;
struct pm860x_touch_pdata *touch;
struct pm860x_power_pdata *power;
struct regulator_init_data *regulator;
struct regulator_init_data *buck1;
struct regulator_init_data *buck2;
struct regulator_init_data *buck3;
struct regulator_init_data *ldo1;
struct regulator_init_data *ldo2;
struct regulator_init_data *ldo3;
struct regulator_init_data *ldo4;
struct regulator_init_data *ldo5;
struct regulator_init_data *ldo6;
struct regulator_init_data *ldo7;
struct regulator_init_data *ldo8;
struct regulator_init_data *ldo9;
struct regulator_init_data *ldo10;
struct regulator_init_data *ldo12;
struct regulator_init_data *ldo_vibrator;
struct regulator_init_data *ldo14;
unsigned short companion_addr; /* I2C address of companion chip */
int companion_addr; /* I2C address of companion chip */
int i2c_port; /* Controlled by GI2C or PI2C */
int irq_mode; /* Clear interrupt by read/write(0/1) */
int irq_base; /* IRQ base number of 88pm860x */
int num_leds;
int num_backlights;
int num_regulators;
};
extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short);
@@ -408,8 +402,4 @@ extern int pm860x_page_bulk_write(struct i2c_client *, int, int,
extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
extern int pm860x_device_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata) __devinit ;
extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ;
#endif /* __LINUX_MFD_88PM860X_H */

129
include/linux/mfd/ab3100.h Normal file
View File

@@ -0,0 +1,129 @@
/*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* AB3100 core access functions
* Author: Linus Walleij <linus.walleij@stericsson.com>
*
*/
#include <linux/regulator/machine.h>
struct device;
#ifndef MFD_AB3100_H
#define MFD_AB3100_H
#define AB3100_P1A 0xc0
#define AB3100_P1B 0xc1
#define AB3100_P1C 0xc2
#define AB3100_P1D 0xc3
#define AB3100_P1E 0xc4
#define AB3100_P1F 0xc5
#define AB3100_P1G 0xc6
#define AB3100_R2A 0xc7
#define AB3100_R2B 0xc8
/*
* AB3100, EVENTA1, A2 and A3 event register flags
* these are catenated into a single 32-bit flag in the code
* for event notification broadcasts.
*/
#define AB3100_EVENTA1_ONSWA (0x01<<16)
#define AB3100_EVENTA1_ONSWB (0x02<<16)
#define AB3100_EVENTA1_ONSWC (0x04<<16)
#define AB3100_EVENTA1_DCIO (0x08<<16)
#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
#define AB3100_EVENTA1_VBUS (0x40<<16)
#define AB3100_EVENTA1_VSET_USB (0x80<<16)
#define AB3100_EVENTA2_READY_TX (0x01<<8)
#define AB3100_EVENTA2_READY_RX (0x02<<8)
#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
#define AB3100_EVENTA2_MIDR (0x20<<8)
#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
#define AB3100_EVENTA2_ALARM (0x80<<8)
#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
/* AB3100, STR register flags */
#define AB3100_STR_ONSWA (0x01)
#define AB3100_STR_ONSWB (0x02)
#define AB3100_STR_ONSWC (0x04)
#define AB3100_STR_DCIO (0x08)
#define AB3100_STR_BOOT_MODE (0x10)
#define AB3100_STR_SIM_OFF (0x20)
#define AB3100_STR_BATT_REMOVAL (0x40)
#define AB3100_STR_VBUS (0x80)
/*
* AB3100 contains 8 regulators, one external regulator controller
* and a buck converter, further the LDO E and buck converter can
* have separate settings if they are in sleep mode, this is
* modeled as a separate regulator.
*/
#define AB3100_NUM_REGULATORS 10
/**
* struct ab3100
* @access_mutex: lock out concurrent accesses to the AB3100 registers
* @dev: pointer to the containing device
* @i2c_client: I2C client for this chip
* @testreg_client: secondary client for test registers
* @chip_name: name of this chip variant
* @chip_id: 8 bit chip ID for this chip variant
* @event_subscribers: event subscribers are listed here
* @startup_events: a copy of the first reading of the event registers
* @startup_events_read: whether the first events have been read
*
* This struct is PRIVATE and devices using it should NOT
* access ANY fields. It is used as a token for calling the
* AB3100 functions.
*/
struct ab3100 {
struct mutex access_mutex;
struct device *dev;
struct i2c_client *i2c_client;
struct i2c_client *testreg_client;
char chip_name[32];
u8 chip_id;
struct blocking_notifier_head event_subscribers;
u8 startup_events[3];
bool startup_events_read;
};
/**
* struct ab3100_platform_data
* Data supplied to initialize board connections to the AB3100
* @reg_constraints: regulator constraints for target board
* the order of these constraints are: LDO A, C, D, E,
* F, G, H, K, EXT and BUCK.
* @reg_initvals: initial values for the regulator registers
* plus two sleep settings for LDO E and the BUCK converter.
* exactly AB3100_NUM_REGULATORS+2 values must be sent in.
* Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
* BUCK sleep, LDO D. (LDO D need to be initialized last.)
* @external_voltage: voltage level of the external regulator.
*/
struct ab3100_platform_data {
struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
u8 reg_initvals[AB3100_NUM_REGULATORS+2];
int external_voltage;
};
int ab3100_event_register(struct ab3100 *ab3100,
struct notifier_block *nb);
int ab3100_event_unregister(struct ab3100 *ab3100,
struct notifier_block *nb);
#endif /* MFD_AB3100_H */

117
include/linux/mfd/abx500.h
View File

@@ -1,12 +1,9 @@
/*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* AB3100 core access functions
* Author: Linus Walleij <linus.walleij@stericsson.com>
*
* ABX500 core access functions.
* The abx500 interface is used for the Analog Baseband chip
* ab3100 and ab8500.
* The abx500 interface is used for the Analog Baseband chips.
*
* Author: Mattias Wallin <mattias.wallin@stericsson.com>
* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
@@ -21,118 +18,6 @@ struct device;
#ifndef MFD_ABX500_H
#define MFD_ABX500_H
#define AB3100_P1A 0xc0
#define AB3100_P1B 0xc1
#define AB3100_P1C 0xc2
#define AB3100_P1D 0xc3
#define AB3100_P1E 0xc4
#define AB3100_P1F 0xc5
#define AB3100_P1G 0xc6
#define AB3100_R2A 0xc7
#define AB3100_R2B 0xc8
/*
* AB3100, EVENTA1, A2 and A3 event register flags
* these are catenated into a single 32-bit flag in the code
* for event notification broadcasts.
*/
#define AB3100_EVENTA1_ONSWA (0x01<<16)
#define AB3100_EVENTA1_ONSWB (0x02<<16)
#define AB3100_EVENTA1_ONSWC (0x04<<16)
#define AB3100_EVENTA1_DCIO (0x08<<16)
#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
#define AB3100_EVENTA1_VBUS (0x40<<16)
#define AB3100_EVENTA1_VSET_USB (0x80<<16)
#define AB3100_EVENTA2_READY_TX (0x01<<8)
#define AB3100_EVENTA2_READY_RX (0x02<<8)
#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
#define AB3100_EVENTA2_MIDR (0x20<<8)
#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
#define AB3100_EVENTA2_ALARM (0x80<<8)
#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
/* AB3100, STR register flags */
#define AB3100_STR_ONSWA (0x01)
#define AB3100_STR_ONSWB (0x02)
#define AB3100_STR_ONSWC (0x04)
#define AB3100_STR_DCIO (0x08)
#define AB3100_STR_BOOT_MODE (0x10)
#define AB3100_STR_SIM_OFF (0x20)
#define AB3100_STR_BATT_REMOVAL (0x40)
#define AB3100_STR_VBUS (0x80)
/*
* AB3100 contains 8 regulators, one external regulator controller
* and a buck converter, further the LDO E and buck converter can
* have separate settings if they are in sleep mode, this is
* modeled as a separate regulator.
*/
#define AB3100_NUM_REGULATORS 10
/**
* struct ab3100
* @access_mutex: lock out concurrent accesses to the AB3100 registers
* @dev: pointer to the containing device
* @i2c_client: I2C client for this chip
* @testreg_client: secondary client for test registers
* @chip_name: name of this chip variant
* @chip_id: 8 bit chip ID for this chip variant
* @event_subscribers: event subscribers are listed here
* @startup_events: a copy of the first reading of the event registers
* @startup_events_read: whether the first events have been read
*
* This struct is PRIVATE and devices using it should NOT
* access ANY fields. It is used as a token for calling the
* AB3100 functions.
*/
struct ab3100 {
struct mutex access_mutex;
struct device *dev;
struct i2c_client *i2c_client;
struct i2c_client *testreg_client;
char chip_name[32];
u8 chip_id;
struct blocking_notifier_head event_subscribers;
u8 startup_events[3];
bool startup_events_read;
};
/**
* struct ab3100_platform_data
* Data supplied to initialize board connections to the AB3100
* @reg_constraints: regulator constraints for target board
* the order of these constraints are: LDO A, C, D, E,
* F, G, H, K, EXT and BUCK.
* @reg_initvals: initial values for the regulator registers
* plus two sleep settings for LDO E and the BUCK converter.
* exactly AB3100_NUM_REGULATORS+2 values must be sent in.
* Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
* BUCK sleep, LDO D. (LDO D need to be initialized last.)
* @external_voltage: voltage level of the external regulator.
*/
struct ab3100_platform_data {
struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
u8 reg_initvals[AB3100_NUM_REGULATORS+2];
int external_voltage;
};
int ab3100_event_register(struct ab3100 *ab3100,
struct notifier_block *nb);
int ab3100_event_unregister(struct ab3100 *ab3100,
struct notifier_block *nb);
/**
* struct abx500_init_setting
* Initial value of the registers for driver to use during setup.

2
include/linux/mfd/abx500/ab8500.h
View File

@@ -341,6 +341,4 @@ static inline int is_ab8500_2p0(struct ab8500 *ab)
return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
}
int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq);
#endif /* MFD_AB8500_H */

40
include/linux/mfd/anatop.h
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@@ -1,40 +0,0 @@
/*
* anatop.h - Anatop MFD driver
*
* Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
* Copyright (C) 2012 Linaro
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_ANATOP_H
#define __LINUX_MFD_ANATOP_H
#include <linux/spinlock.h>
/**
* anatop - MFD data
* @ioreg: ioremap register
* @reglock: spinlock for register read/write
*/
struct anatop {
void *ioreg;
spinlock_t reglock;
};
extern u32 anatop_read_reg(struct anatop *, u32);
extern void anatop_write_reg(struct anatop *, u32, u32, u32);
#endif /* __LINUX_MFD_ANATOP_H */

94
include/linux/mfd/da9055/core.h Normal file
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@@ -0,0 +1,94 @@
/*
* da9055 declarations for DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __DA9055_CORE_H
#define __DA9055_CORE_H
#include <linux/interrupt.h>
#include <linux/regmap.h>
/*
* PMIC IRQ
*/
#define DA9055_IRQ_ALARM 0x01
#define DA9055_IRQ_TICK 0x02
#define DA9055_IRQ_NONKEY 0x00
#define DA9055_IRQ_REGULATOR 0x0B
#define DA9055_IRQ_HWMON 0x03
struct da9055_pdata;
struct da9055 {
struct regmap *regmap;
struct regmap_irq_chip_data *irq_data;
struct device *dev;
struct i2c_client *i2c_client;
int irq_base;
int chip_irq;
};
/* Device I/O */
static inline int da9055_reg_read(struct da9055 *da9055, unsigned char reg)
{
int val, ret;
ret = regmap_read(da9055->regmap, reg, &val);
if (ret < 0)
return ret;
return val;
}
static inline int da9055_reg_write(struct da9055 *da9055, unsigned char reg,
unsigned char val)
{
return regmap_write(da9055->regmap, reg, val);
}
static inline int da9055_group_read(struct da9055 *da9055, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt);
}
static inline int da9055_group_write(struct da9055 *da9055, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
return regmap_raw_write(da9055->regmap, reg, val, reg_cnt);
}
static inline int da9055_reg_update(struct da9055 *da9055, unsigned char reg,
unsigned char bit_mask,
unsigned char reg_val)
{
return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val);
}
/* Generic Device API */
int da9055_device_init(struct da9055 *da9055);
void da9055_device_exit(struct da9055 *da9055);
extern struct regmap_config da9055_regmap_config;
#endif /* __DA9055_CORE_H */

32
include/linux/mfd/da9055/pdata.h Normal file
View File

@@ -0,0 +1,32 @@
/* Copyright (C) 2012 Dialog Semiconductor Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __DA9055_PDATA_H
#define __DA9055_PDATA_H
#define DA9055_MAX_REGULATORS 8
struct da9055;
enum gpio_select {
NO_GPIO = 0,
GPIO_1,
GPIO_2
};
struct da9055_pdata {
int (*init) (struct da9055 *da9055);
int irq_base;
int gpio_base;
struct regulator_init_data *regulators[DA9055_MAX_REGULATORS];
bool reset_enable; /* Enable RTC in RESET Mode */
enum gpio_select *gpio_rsel; /* Select regulator set thru GPIO 1/2 */
enum gpio_select *gpio_ren; /* Enable regulator thru GPIO 1/2 */
};
#endif /* __DA9055_PDATA_H */

699
include/linux/mfd/da9055/reg.h Normal file
View File

@@ -0,0 +1,699 @@
/*
* DA9055 declarations for DA9055 PMICs.
*
* Copyright(c) 2012 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __DA9055_REG_H
#define __DA9055_REG_H
/*
* PMIC registers
*/
/* PAGE0 */
#define DA9055_REG_PAGE_CON 0x00
/* System Control and Event Registers */
#define DA9055_REG_STATUS_A 0x01
#define DA9055_REG_STATUS_B 0x02
#define DA9055_REG_FAULT_LOG 0x03
#define DA9055_REG_EVENT_A 0x04
#define DA9055_REG_EVENT_B 0x05
#define DA9055_REG_EVENT_C 0x06
#define DA9055_REG_IRQ_MASK_A 0x07
#define DA9055_REG_IRQ_MASK_B 0x08
#define DA9055_REG_IRQ_MASK_C 0x09
#define DA9055_REG_CONTROL_A 0x0A
#define DA9055_REG_CONTROL_B 0x0B
#define DA9055_REG_CONTROL_C 0x0C
#define DA9055_REG_CONTROL_D 0x0D
#define DA9055_REG_CONTROL_E 0x0E
#define DA9055_REG_PD_DIS 0x0F
/* GPIO Control Registers */
#define DA9055_REG_GPIO0_1 0x10
#define DA9055_REG_GPIO2 0x11
#define DA9055_REG_GPIO_MODE0_2 0x12
/* Regulator Control Registers */
#define DA9055_REG_BCORE_CONT 0x13
#define DA9055_REG_BMEM_CONT 0x14
#define DA9055_REG_LDO1_CONT 0x15
#define DA9055_REG_LDO2_CONT 0x16
#define DA9055_REG_LDO3_CONT 0x17
#define DA9055_REG_LDO4_CONT 0x18
#define DA9055_REG_LDO5_CONT 0x19
#define DA9055_REG_LDO6_CONT 0x1A
/* GP-ADC Control Registers */
#define DA9055_REG_ADC_MAN 0x1B
#define DA9055_REG_ADC_CONT 0x1C
#define DA9055_REG_VSYS_MON 0x1D
#define DA9055_REG_ADC_RES_L 0x1E
#define DA9055_REG_ADC_RES_H 0x1F
#define DA9055_REG_VSYS_RES 0x20
#define DA9055_REG_ADCIN1_RES 0x21
#define DA9055_REG_ADCIN2_RES 0x22
#define DA9055_REG_ADCIN3_RES 0x23
/* Sequencer Control Registers */
#define DA9055_REG_EN_32K 0x35
/* Regulator Setting Registers */
#define DA9055_REG_BUCK_LIM 0x37
#define DA9055_REG_BCORE_MODE 0x38
#define DA9055_REG_VBCORE_A 0x39
#define DA9055_REG_VBMEM_A 0x3A
#define DA9055_REG_VLDO1_A 0x3B
#define DA9055_REG_VLDO2_A 0x3C
#define DA9055_REG_VLDO3_A 0x3D
#define DA9055_REG_VLDO4_A 0x3E
#define DA9055_REG_VLDO5_A 0x3F
#define DA9055_REG_VLDO6_A 0x40
#define DA9055_REG_VBCORE_B 0x41
#define DA9055_REG_VBMEM_B 0x42
#define DA9055_REG_VLDO1_B 0x43
#define DA9055_REG_VLDO2_B 0x44
#define DA9055_REG_VLDO3_B 0x45
#define DA9055_REG_VLDO4_B 0x46
#define DA9055_REG_VLDO5_B 0x47
#define DA9055_REG_VLDO6_B 0x48
/* GP-ADC Threshold Registers */
#define DA9055_REG_AUTO1_HIGH 0x49
#define DA9055_REG_AUTO1_LOW 0x4A
#define DA9055_REG_AUTO2_HIGH 0x4B
#define DA9055_REG_AUTO2_LOW 0x4C
#define DA9055_REG_AUTO3_HIGH 0x4D
#define DA9055_REG_AUTO3_LOW 0x4E
/* OTP */
#define DA9055_REG_OPT_COUNT 0x50
#define DA9055_REG_OPT_ADDR 0x51
#define DA9055_REG_OPT_DATA 0x52
/* RTC Calendar and Alarm Registers */
#define DA9055_REG_COUNT_S 0x53
#define DA9055_REG_COUNT_MI 0x54
#define DA9055_REG_COUNT_H 0x55
#define DA9055_REG_COUNT_D 0x56
#define DA9055_REG_COUNT_MO 0x57
#define DA9055_REG_COUNT_Y 0x58
#define DA9055_REG_ALARM_MI 0x59
#define DA9055_REG_ALARM_H 0x5A
#define DA9055_REG_ALARM_D 0x5B
#define DA9055_REG_ALARM_MO 0x5C
#define DA9055_REG_ALARM_Y 0x5D
#define DA9055_REG_SECOND_A 0x5E
#define DA9055_REG_SECOND_B 0x5F
#define DA9055_REG_SECOND_C 0x60
#define DA9055_REG_SECOND_D 0x61
/* Customer Trim and Configuration */
#define DA9055_REG_T_OFFSET 0x63
#define DA9055_REG_INTERFACE 0x64
#define DA9055_REG_CONFIG_A 0x65
#define DA9055_REG_CONFIG_B 0x66
#define DA9055_REG_CONFIG_C 0x67
#define DA9055_REG_CONFIG_D 0x68
#define DA9055_REG_CONFIG_E 0x69
#define DA9055_REG_TRIM_CLDR 0x6F
/* General Purpose Registers */
#define DA9055_REG_GP_ID_0 0x70
#define DA9055_REG_GP_ID_1 0x71
#define DA9055_REG_GP_ID_2 0x72
#define DA9055_REG_GP_ID_3 0x73
#define DA9055_REG_GP_ID_4 0x74
#define DA9055_REG_GP_ID_5 0x75
#define DA9055_REG_GP_ID_6 0x76
#define DA9055_REG_GP_ID_7 0x77
#define DA9055_REG_GP_ID_8 0x78
#define DA9055_REG_GP_ID_9 0x79
#define DA9055_REG_GP_ID_10 0x7A
#define DA9055_REG_GP_ID_11 0x7B
#define DA9055_REG_GP_ID_12 0x7C
#define DA9055_REG_GP_ID_13 0x7D
#define DA9055_REG_GP_ID_14 0x7E
#define DA9055_REG_GP_ID_15 0x7F
#define DA9055_REG_GP_ID_16 0x80
#define DA9055_REG_GP_ID_17 0x81
#define DA9055_REG_GP_ID_18 0x82
#define DA9055_REG_GP_ID_19 0x83
#define DA9055_MAX_REGISTER_CNT DA9055_REG_GP_ID_19
/*
* PMIC registers bits
*/
/* DA9055_REG_PAGE_CON (addr=0x00) */
#define DA9055_PAGE_WRITE_MODE (0<<6)
#define DA9055_REPEAT_WRITE_MODE (1<<6)
/* DA9055_REG_STATUS_A (addr=0x01) */
#define DA9055_NOKEY_STS 0x01
#define DA9055_WAKE_STS 0x02
#define DA9055_DVC_BUSY_STS 0x04
#define DA9055_COMP1V2_STS 0x08
#define DA9055_NJIG_STS 0x10
#define DA9055_LDO5_LIM_STS 0x20
#define DA9055_LDO6_LIM_STS 0x40
/* DA9055_REG_STATUS_B (addr=0x02) */
#define DA9055_GPI0_STS 0x01
#define DA9055_GPI1_STS 0x02
#define DA9055_GPI2_STS 0x04
/* DA9055_REG_FAULT_LOG (addr=0x03) */
#define DA9055_TWD_ERROR_FLG 0x01
#define DA9055_POR_FLG 0x02
#define DA9055_VDD_FAULT_FLG 0x04
#define DA9055_VDD_START_FLG 0x08
#define DA9055_TEMP_CRIT_FLG 0x10
#define DA9055_KEY_RESET_FLG 0x20
#define DA9055_WAIT_SHUT_FLG 0x80
/* DA9055_REG_EVENT_A (addr=0x04) */
#define DA9055_NOKEY_EINT 0x01
#define DA9055_ALARM_EINT 0x02
#define DA9055_TICK_EINT 0x04
#define DA9055_ADC_RDY_EINT 0x08
#define DA9055_SEQ_RDY_EINT 0x10
#define DA9055_EVENTS_B_EINT 0x20
#define DA9055_EVENTS_C_EINT 0x40
/* DA9055_REG_EVENT_B (addr=0x05) */
#define DA9055_E_WAKE_EINT 0x01
#define DA9055_E_TEMP_EINT 0x02
#define DA9055_E_COMP1V2_EINT 0x04
#define DA9055_E_LDO_LIM_EINT 0x08
#define DA9055_E_NJIG_EINT 0x20
#define DA9055_E_VDD_MON_EINT 0x40
#define DA9055_E_VDD_WARN_EINT 0x80
/* DA9055_REG_EVENT_C (addr=0x06) */
#define DA9055_E_GPI0_EINT 0x01
#define DA9055_E_GPI1_EINT 0x02
#define DA9055_E_GPI2_EINT 0x04
/* DA9055_REG_IRQ_MASK_A (addr=0x07) */
#define DA9055_M_NONKEY_EINT 0x01
#define DA9055_M_ALARM_EINT 0x02
#define DA9055_M_TICK_EINT 0x04
#define DA9055_M_ADC_RDY_EINT 0x08
#define DA9055_M_SEQ_RDY_EINT 0x10
/* DA9055_REG_IRQ_MASK_B (addr=0x08) */
#define DA9055_M_WAKE_EINT 0x01
#define DA9055_M_TEMP_EINT 0x02
#define DA9055_M_COMP_1V2_EINT 0x04
#define DA9055_M_LDO_LIM_EINT 0x08
#define DA9055_M_NJIG_EINT 0x20
#define DA9055_M_VDD_MON_EINT 0x40
#define DA9055_M_VDD_WARN_EINT 0x80
/* DA9055_REG_IRQ_MASK_C (addr=0x09) */
#define DA9055_M_GPI0_EINT 0x01
#define DA9055_M_GPI1_EINT 0x02
#define DA9055_M_GPI2_EINT 0x04
/* DA9055_REG_CONTROL_A (addr=0xA) */
#define DA9055_DEBOUNCING_SHIFT 0x00
#define DA9055_DEBOUNCING_MASK 0x07
#define DA9055_NRES_MODE_SHIFT 0x03
#define DA9055_NRES_MODE_MASK 0x08
#define DA9055_SLEW_RATE_SHIFT 0x04
#define DA9055_SLEW_RATE_MASK 0x30
#define DA9055_NOKEY_LOCK_SHIFT 0x06
#define DA9055_NOKEY_LOCK_MASK 0x40
/* DA9055_REG_CONTROL_B (addr=0xB) */
#define DA9055_RTC_MODE_PD 0x01
#define DA9055_RTC_MODE_SD_SHIFT 0x01
#define DA9055_RTC_MODE_SD 0x02
#define DA9055_RTC_EN 0x04
#define DA9055_ECO_MODE_SHIFT 0x03
#define DA9055_ECO_MODE_MASK 0x08
#define DA9055_TWDSCALE_SHIFT 4
#define DA9055_TWDSCALE_MASK 0x70
#define DA9055_V_LOCK_SHIFT 0x07
#define DA9055_V_LOCK_MASK 0x80
/* DA9055_REG_CONTROL_C (addr=0xC) */
#define DA9055_SYSTEM_EN_SHIFT 0x00
#define DA9055_SYSTEM_EN_MASK 0x01
#define DA9055_POWERN_EN_SHIFT 0x01
#define DA9055_POWERN_EN_MASK 0x02
#define DA9055_POWER1_EN_SHIFT 0x02
#define DA9055_POWER1_EN_MASK 0x04
/* DA9055_REG_CONTROL_D (addr=0xD) */
#define DA9055_STANDBY_SHIFT 0x02
#define DA9055_STANDBY_MASK 0x08
#define DA9055_AUTO_BOOT_SHIFT 0x03
#define DA9055_AUTO_BOOT_MASK 0x04
/* DA9055_REG_CONTROL_E (addr=0xE) */
#define DA9055_WATCHDOG_SHIFT 0x00
#define DA9055_WATCHDOG_MASK 0x01
#define DA9055_SHUTDOWN_SHIFT 0x01
#define DA9055_SHUTDOWN_MASK 0x02
#define DA9055_WAKE_UP_SHIFT 0x02
#define DA9055_WAKE_UP_MASK 0x04
/* DA9055_REG_GPIO (addr=0x10/0x11) */
#define DA9055_GPIO0_PIN_SHIFT 0x00
#define DA9055_GPIO0_PIN_MASK 0x03
#define DA9055_GPIO0_TYPE_SHIFT 0x02
#define DA9055_GPIO0_TYPE_MASK 0x04
#define DA9055_GPIO0_WEN_SHIFT 0x03
#define DA9055_GPIO0_WEN_MASK 0x08
#define DA9055_GPIO1_PIN_SHIFT 0x04
#define DA9055_GPIO1_PIN_MASK 0x30
#define DA9055_GPIO1_TYPE_SHIFT 0x06
#define DA9055_GPIO1_TYPE_MASK 0x40
#define DA9055_GPIO1_WEN_SHIFT 0x07
#define DA9055_GPIO1_WEN_MASK 0x80
#define DA9055_GPIO2_PIN_SHIFT 0x00
#define DA9055_GPIO2_PIN_MASK 0x30
#define DA9055_GPIO2_TYPE_SHIFT 0x02
#define DA9055_GPIO2_TYPE_MASK 0x04
#define DA9055_GPIO2_WEN_SHIFT 0x03
#define DA9055_GPIO2_WEN_MASK 0x08
/* DA9055_REG_GPIO_MODE (addr=0x12) */
#define DA9055_GPIO0_MODE_SHIFT 0x00
#define DA9055_GPIO0_MODE_MASK 0x01
#define DA9055_GPIO1_MODE_SHIFT 0x01
#define DA9055_GPIO1_MODE_MASK 0x02
#define DA9055_GPIO2_MODE_SHIFT 0x02
#define DA9055_GPIO2_MODE_MASK 0x04
/* DA9055_REG_BCORE_CONT (addr=0x13) */
#define DA9055_BCORE_EN_SHIFT 0x00
#define DA9055_BCORE_EN_MASK 0x01
#define DA9055_BCORE_GPI_SHIFT 0x01
#define DA9055_BCORE_GPI_MASK 0x02
#define DA9055_BCORE_PD_DIS_SHIFT 0x03
#define DA9055_BCORE_PD_DIS_MASK 0x04
#define DA9055_VBCORE_SEL_SHIFT 0x04
#define DA9055_SEL_REG_A 0x0
#define DA9055_SEL_REG_B 0x10
#define DA9055_VBCORE_SEL_MASK 0x10
#define DA9055_V_GPI_MASK 0x60
#define DA9055_V_GPI_SHIFT 0x05
#define DA9055_E_GPI_MASK 0x06
#define DA9055_E_GPI_SHIFT 0x01
#define DA9055_VBCORE_GPI_SHIFT 0x05
#define DA9055_VBCORE_GPI_MASK 0x60
#define DA9055_BCORE_CONF_SHIFT 0x07
#define DA9055_BCORE_CONF_MASK 0x80
/* DA9055_REG_BMEM_CONT (addr=0x14) */
#define DA9055_BMEM_EN_SHIFT 0x00
#define DA9055_BMEM_EN_MASK 0x01
#define DA9055_BMEM_GPI_SHIFT 0x01
#define DA9055_BMEM_GPI_MASK 0x06
#define DA9055_BMEM_PD_DIS_SHIFT 0x03
#define DA9055_BMEM_PD_DIS_MASK 0x08
#define DA9055_VBMEM_SEL_SHIT 0x04
#define DA9055_VBMEM_SEL_VBMEM_A (0<<4)
#define DA9055_VBMEM_SEL_VBMEM_B (1<<4)
#define DA9055_VBMEM_SEL_MASK 0x10
#define DA9055_VBMEM_GPI_SHIFT 0x05
#define DA9055_VBMEM_GPI_MASK 0x60
#define DA9055_BMEM_CONF_SHIFT 0x07
#define DA9055_BMEM_CONF_MASK 0x80
/* DA9055_REG_LDO_CONT (addr=0x15-0x1A) */
#define DA9055_LDO_EN_SHIFT 0x00
#define DA9055_LDO_EN_MASK 0x01
#define DA9055_LDO_GPI_SHIFT 0x01
#define DA9055_LDO_GPI_MASK 0x06
#define DA9055_LDO_PD_DIS_SHIFT 0x03
#define DA9055_LDO_PD_DIS_MASK 0x08
#define DA9055_VLDO_SEL_SHIFT 0x04
#define DA9055_VLDO_SEL_MASK 0x10
#define DA9055_VLDO_SEL_VLDO_A 0x00
#define DA9055_VLDO_SEL_VLDO_B 0x01
#define DA9055_VLDO_GPI_SHIFT 0x05
#define DA9055_VLDO_GPI_MASK 0x60
#define DA9055_LDO_CONF_SHIFT 0x07
#define DA9055_LDO_CONF_MASK 0x80
#define DA9055_REGUALTOR_SET_A 0x00
#define DA9055_REGUALTOR_SET_B 0x10
/* DA9055_REG_ADC_MAN (addr=0x1B) */
#define DA9055_ADC_MUX_SHIFT 0
#define DA9055_ADC_MUX_MASK 0xF
#define DA9055_ADC_MUX_VSYS 0x0
#define DA9055_ADC_MUX_ADCIN1 0x01
#define DA9055_ADC_MUX_ADCIN2 0x02
#define DA9055_ADC_MUX_ADCIN3 0x03
#define DA9055_ADC_MUX_T_SENSE 0x04
#define DA9055_ADC_MAN_SHIFT 0x04
#define DA9055_ADC_MAN_CONV 0x10
#define DA9055_ADC_LSB_MASK 0X03
#define DA9055_ADC_MODE_MASK 0x20
#define DA9055_ADC_MODE_SHIFT 5
#define DA9055_ADC_MODE_1MS (1<<5)
#define DA9055_COMP1V2_EN_SHIFT 7
/* DA9055_REG_ADC_CONT (addr=0x1C) */
#define DA9055_ADC_AUTO_VSYS_EN_SHIFT 0
#define DA9055_ADC_AUTO_AD1_EN_SHIFT 1
#define DA9055_ADC_AUTO_AD2_EN_SHIFT 2
#define DA9055_ADC_AUTO_AD3_EN_SHIFT 3
#define DA9055_ADC_ISRC_EN_SHIFT 4
#define DA9055_ADC_ADCIN1_DEB_SHIFT 5
#define DA9055_ADC_ADCIN2_DEB_SHIFT 6
#define DA9055_ADC_ADCIN3_DEB_SHIFT 7
#define DA9055_AD1_ISRC_MASK 0x10
#define DA9055_AD1_ISRC_SHIFT 4
/* DA9055_REG_VSYS_MON (addr=0x1D) */
#define DA9055_VSYS_VAL_SHIFT 0
#define DA9055_VSYS_VAL_MASK 0xFF
#define DA9055_VSYS_VAL_BASE 0x00
#define DA9055_VSYS_VAL_MAX DA9055_VSYS_VAL_MASK
#define DA9055_VSYS_VOLT_BASE 2500
#define DA9055_VSYS_VOLT_INC 10
#define DA9055_VSYS_STEPS 255
#define DA9055_VSYS_VOLT_MIN 2500
/* DA9044_REG_XXX_RES (addr=0x20-0x23) */
#define DA9055_ADC_VAL_SHIFT 0
#define DA9055_ADC_VAL_MASK 0xFF
#define DA9055_ADC_VAL_BASE 0x00
#define DA9055_ADC_VAL_MAX DA9055_ADC_VAL_MASK
#define DA9055_ADC_VOLT_BASE 0
#define DA9055_ADC_VSYS_VOLT_BASE 2500
#define DA9055_ADC_VOLT_INC 10
#define DA9055_ADC_VSYS_VOLT_INC 12
#define DA9055_ADC_STEPS 255
/* DA9055_REG_EN_32K (addr=0x35)*/
#define DA9055_STARTUP_TIME_MASK 0x07
#define DA9055_STARTUP_TIME_0S 0x0
#define DA9055_STARTUP_TIME_0_52S 0x1
#define DA9055_STARTUP_TIME_1S 0x2
#define DA9055_CRYSTAL_EN 0x08
#define DA9055_DELAY_MODE_EN 0x10
#define DA9055_OUT_CLCK_GATED 0x20
#define DA9055_RTC_CLOCK_GATED 0x40
#define DA9055_EN_32KOUT_BUF 0x80
/* DA9055_REG_RESET (addr=0x36) */
/* Timer up to 31.744 ms */
#define DA9055_RESET_TIMER_VAL_SHIFT 0
#define DA9055_RESET_LOW_VAL_MASK 0x3F
#define DA9055_RESET_LOW_VAL_BASE 0
#define DA9055_RESET_LOW_VAL_MAX DA9055_RESET_LOW_VAL_MASK
#define DA9055_RESET_US_LOW_BASE 1024 /* min val in units of us */
#define DA9055_RESET_US_LOW_INC 1024 /* inc val in units of us */
#define DA9055_RESET_US_LOW_STEP 30
/* Timer up to 1048.576ms */
#define DA9055_RESET_HIGH_VAL_MASK 0x3F
#define DA9055_RESET_HIGH_VAL_BASE 0
#define DA9055_RESET_HIGH_VAL_MAX DA9055_RESET_HIGH_VAL_MASK
#define DA9055_RESET_US_HIGH_BASE 32768 /* min val in units of us */
#define DA9055_RESET_US_HIGH_INC 32768 /* inv val in units of us */
#define DA9055_RESET_US_HIGH_STEP 31
/* DA9055_REG_BUCK_ILIM (addr=0x37)*/
#define DA9055_BMEM_ILIM_SHIFT 0
#define DA9055_ILIM_MASK 0x3
#define DA9055_ILIM_500MA 0x0
#define DA9055_ILIM_600MA 0x1
#define DA9055_ILIM_700MA 0x2
#define DA9055_ILIM_800MA 0x3
#define DA9055_BCORE_ILIM_SHIFT 2
/* DA9055_REG_BCORE_MODE (addr=0x38) */
#define DA9055_BMEM_MODE_SHIFT 0
#define DA9055_MODE_MASK 0x3
#define DA9055_MODE_AB 0x0
#define DA9055_MODE_SLEEP 0x1
#define DA9055_MODE_SYNCHRO 0x2
#define DA9055_MODE_AUTO 0x3
#define DA9055_BCORE_MODE_SHIFT 2
/* DA9055_REG_VBCORE_A/B (addr=0x39/0x41)*/
#define DA9055_VBCORE_VAL_SHIFT 0
#define DA9055_VBCORE_VAL_MASK 0x3F
#define DA9055_VBCORE_VAL_BASE 0x09
#define DA9055_VBCORE_VAL_MAX DA9055_VBCORE_VAL_MASK
#define DA9055_VBCORE_VOLT_BASE 750
#define DA9055_VBCORE_VOLT_INC 25
#define DA9055_VBCORE_STEPS 53
#define DA9055_VBCORE_VOLT_MIN DA9055_VBCORE_VOLT_BASE
#define DA9055_BCORE_SL_SYNCHRO (0<<7)
#define DA9055_BCORE_SL_SLEEP (1<<7)
/* DA9055_REG_VBMEM_A/B (addr=0x3A/0x42)*/
#define DA9055_VBMEM_VAL_SHIFT 0
#define DA9055_VBMEM_VAL_MASK 0x3F
#define DA9055_VBMEM_VAL_BASE 0x00
#define DA9055_VBMEM_VAL_MAX DA9055_VBMEM_VAL_MASK
#define DA9055_VBMEM_VOLT_BASE 925
#define DA9055_VBMEM_VOLT_INC 25
#define DA9055_VBMEM_STEPS 63
#define DA9055_VBMEM_VOLT_MIN DA9055_VBMEM_VOLT_BASE
#define DA9055_BCMEM_SL_SYNCHRO (0<<7)
#define DA9055_BCMEM_SL_SLEEP (1<<7)
/* DA9055_REG_VLDO (addr=0x3B-0x40/0x43-0x48)*/
#define DA9055_VLDO_VAL_SHIFT 0
#define DA9055_VLDO_VAL_MASK 0x3F
#define DA9055_VLDO6_VAL_MASK 0x7F
#define DA9055_VLDO_VAL_BASE 0x02
#define DA9055_VLDO2_VAL_BASE 0x03
#define DA9055_VLDO6_VAL_BASE 0x00
#define DA9055_VLDO_VAL_MAX DA9055_VLDO_VAL_MASK
#define DA9055_VLDO6_VAL_MAX DA9055_VLDO6_VAL_MASK
#define DA9055_VLDO_VOLT_BASE 900
#define DA9055_VLDO_VOLT_INC 50
#define DA9055_VLDO6_VOLT_INC 20
#define DA9055_VLDO_STEPS 48
#define DA9055_VLDO5_STEPS 37
#define DA9055_VLDO6_STEPS 120
#define DA9055_VLDO_VOLT_MIN DA9055_VLDO_VOLT_BASE
#define DA9055_LDO_MODE_SHIFT 7
#define DA9055_LDO_SL_NORMAL 0
#define DA9055_LDO_SL_SLEEP 1
/* DA9055_REG_OTP_CONT (addr=0x50) */
#define DA9055_OTP_TIM_NORMAL (0<<0)
#define DA9055_OTP_TIM_MARGINAL (1<<0)
#define DA9055_OTP_GP_RD_SHIFT 1
#define DA9055_OTP_APPS_RD_SHIFT 2
#define DA9055_PC_DONE_SHIFT 3
#define DA9055_OTP_GP_LOCK_SHIFT 4
#define DA9055_OTP_APPS_LOCK_SHIFT 5
#define DA9055_OTP_CONF_LOCK_SHIFT 6
#define DA9055_OTP_WRITE_DIS_SHIFT 7
/* DA9055_REG_COUNT_S (addr=0x53) */
#define DA9055_RTC_SEC 0x3F
#define DA9055_RTC_MONITOR_EN 0x40
#define DA9055_RTC_READ 0x80
/* DA9055_REG_COUNT_MI (addr=0x54) */
#define DA9055_RTC_MIN 0x3F
/* DA9055_REG_COUNT_H (addr=0x55) */
#define DA9055_RTC_HOUR 0x1F
/* DA9055_REG_COUNT_D (addr=0x56) */
#define DA9055_RTC_DAY 0x1F
/* DA9055_REG_COUNT_MO (addr=0x57) */
#define DA9055_RTC_MONTH 0x0F
/* DA9055_REG_COUNT_Y (addr=0x58) */
#define DA9055_RTC_YEAR 0x3F
#define DA9055_RTC_YEAR_BASE 2000
/* DA9055_REG_ALARM_MI (addr=0x59) */
#define DA9055_RTC_ALM_MIN 0x3F
#define DA9055_ALARM_STATUS_SHIFT 6
#define DA9055_ALARM_STATUS_MASK 0x3
#define DA9055_ALARM_STATUS_NO_ALARM 0x0
#define DA9055_ALARM_STATUS_TICK 0x1
#define DA9055_ALARM_STATUS_TIMER_ALARM 0x2
#define DA9055_ALARM_STATUS_BOTH 0x3
/* DA9055_REG_ALARM_H (addr=0x5A) */
#define DA9055_RTC_ALM_HOUR 0x1F
/* DA9055_REG_ALARM_D (addr=0x5B) */
#define DA9055_RTC_ALM_DAY 0x1F
/* DA9055_REG_ALARM_MO (addr=0x5C) */
#define DA9055_RTC_ALM_MONTH 0x0F
#define DA9055_RTC_TICK_WAKE_MASK 0x20
#define DA9055_RTC_TICK_WAKE_SHIFT 5
#define DA9055_RTC_TICK_TYPE 0x10
#define DA9055_RTC_TICK_TYPE_SHIFT 0x4
#define DA9055_RTC_TICK_SEC 0x0
#define DA9055_RTC_TICK_MIN 0x1
#define DA9055_ALARAM_TICK_WAKE 0x20
/* DA9055_REG_ALARM_Y (addr=0x5D) */
#define DA9055_RTC_TICK_EN 0x80
#define DA9055_RTC_ALM_EN 0x40
#define DA9055_RTC_TICK_ALM_MASK 0xC0
#define DA9055_RTC_ALM_YEAR 0x3F
/* DA9055_REG_TRIM_CLDR (addr=0x62) */
#define DA9055_TRIM_32K_SHIFT 0
#define DA9055_TRIM_32K_MASK 0x7F
#define DA9055_TRIM_DECREMENT (1<<7)
#define DA9055_TRIM_INCREMENT (0<<7)
#define DA9055_TRIM_VAL_BASE 0x0
#define DA9055_TRIM_PPM_BASE 0x0 /* min val in units of 0.1PPM */
#define DA9055_TRIM_PPM_INC 19 /* min inc in units of 0.1PPM */
#define DA9055_TRIM_STEPS 127
/* DA9055_REG_CONFIG_A (addr=0x65) */
#define DA9055_PM_I_V_VDDCORE (0<<0)
#define DA9055_PM_I_V_VDD_IO (1<<0)
#define DA9055_VDD_FAULT_TYPE_ACT_LOW (0<<1)
#define DA9055_VDD_FAULT_TYPE_ACT_HIGH (1<<1)
#define DA9055_PM_O_TYPE_PUSH_PULL (0<<2)
#define DA9055_PM_O_TYPE_OPEN_DRAIN (1<<2)
#define DA9055_IRQ_TYPE_ACT_LOW (0<<3)
#define DA9055_IRQ_TYPE_ACT_HIGH (1<<3)
#define DA9055_NIRQ_MODE_IMM (0<<4)
#define DA9055_NIRQ_MODE_ACTIVE (1<<4)
#define DA9055_GPI_V_VDDCORE (0<<5)
#define DA9055_GPI_V_VDD_IO (1<<5)
#define DA9055_PM_IF_V_VDDCORE (0<<6)
#define DA9055_PM_IF_V_VDD_IO (1<<6)
/* DA9055_REG_CONFIG_B (addr=0x66) */
#define DA9055_VDD_FAULT_VAL_SHIFT 0
#define DA9055_VDD_FAULT_VAL_MASK 0xF
#define DA9055_VDD_FAULT_VAL_BASE 0x0
#define DA9055_VDD_FAULT_VAL_MAX DA9055_VDD_FAULT_VAL_MASK
#define DA9055_VDD_FAULT_VOLT_BASE 2500
#define DA9055_VDD_FAULT_VOLT_INC 50
#define DA9055_VDD_FAULT_STEPS 15
#define DA9055_VDD_HYST_VAL_SHIFT 4
#define DA9055_VDD_HYST_VAL_MASK 0x7
#define DA9055_VDD_HYST_VAL_BASE 0x0
#define DA9055_VDD_HYST_VAL_MAX DA9055_VDD_HYST_VAL_MASK
#define DA9055_VDD_HYST_VOLT_BASE 100
#define DA9055_VDD_HYST_VOLT_INC 50
#define DA9055_VDD_HYST_STEPS 7
#define DA9055_VDD_HYST_VOLT_MIN DA9055_VDD_HYST_VOLT_BASE
#define DA9055_VDD_FAULT_EN_SHIFT 7
/* DA9055_REG_CONFIG_C (addr=0x67) */
#define DA9055_BCORE_CLK_INV_SHIFT 0
#define DA9055_BMEM_CLK_INV_SHIFT 1
#define DA9055_NFAULT_CONF_SHIFT 2
#define DA9055_LDO_SD_SHIFT 4
#define DA9055_LDO5_BYP_SHIFT 6
#define DA9055_LDO6_BYP_SHIFT 7
/* DA9055_REG_CONFIG_D (addr=0x68) */
#define DA9055_NONKEY_PIN_SHIFT 0
#define DA9055_NONKEY_PIN_MASK 0x3
#define DA9055_NONKEY_PIN_PORT_MODE 0x0
#define DA9055_NONKEY_PIN_KEY_MODE 0x1
#define DA9055_NONKEY_PIN_MULTI_FUNC 0x2
#define DA9055_NONKEY_PIN_DEDICT 0x3
#define DA9055_NONKEY_SD_SHIFT 2
#define DA9055_KEY_DELAY_SHIFT 3
#define DA9055_KEY_DELAY_MASK 0x3
#define DA9055_KEY_DELAY_4S 0x0
#define DA9055_KEY_DELAY_6S 0x1
#define DA9055_KEY_DELAY_8S 0x2
#define DA9055_KEY_DELAY_10S 0x3
/* DA9055_REG_CONFIG_E (addr=0x69) */
#define DA9055_GPIO_PUPD_PULL_UP 0x0
#define DA9055_GPIO_PUPD_OPEN_DRAIN 0x1
#define DA9055_GPIO0_PUPD_SHIFT 0
#define DA9055_GPIO1_PUPD_SHIFT 1
#define DA9055_GPIO2_PUPD_SHIFT 2
#define DA9055_UVOV_DELAY_SHIFT 4
#define DA9055_UVOV_DELAY_MASK 0x3
#define DA9055_RESET_DURATION_SHIFT 6
#define DA9055_RESET_DURATION_MASK 0x3
#define DA9055_RESET_DURATION_0MS 0x0
#define DA9055_RESET_DURATION_100MS 0x1
#define DA9055_RESET_DURATION_500MS 0x2
#define DA9055_RESET_DURATION_1000MS 0x3
/* DA9055_REG_MON_REG_1 (addr=0x6A) */
#define DA9055_MON_THRES_SHIFT 0
#define DA9055_MON_THRES_MASK 0x3
#define DA9055_MON_RES_SHIFT 2
#define DA9055_MON_DEB_SHIFT 3
#define DA9055_MON_MODE_SHIFT 4
#define DA9055_MON_MODE_MASK 0x3
#define DA9055_START_MAX_SHIFT 6
#define DA9055_START_MAX_MASK 0x3
/* DA9055_REG_MON_REG_2 (addr=0x6B) */
#define DA9055_LDO1_MON_EN_SHIFT 0
#define DA9055_LDO2_MON_EN_SHIFT 1
#define DA9055_LDO3_MON_EN_SHIFT 2
#define DA9055_LDO4_MON_EN_SHIFT 3
#define DA9055_LDO5_MON_EN_SHIFT 4
#define DA9055_LDO6_MON_EN_SHIFT 5
#define DA9055_BCORE_MON_EN_SHIFT 6
#define DA9055_BMEM_MON_EN_SHIFT 7
/* DA9055_REG_CONFIG_F (addr=0x6C) */
#define DA9055_LDO1_DEF_SHIFT 0
#define DA9055_LDO2_DEF_SHIFT 1
#define DA9055_LDO3_DEF_SHIFT 2
#define DA9055_LDO4_DEF_SHIFT 3
#define DA9055_LDO5_DEF_SHIFT 4
#define DA9055_LDO6_DEF_SHIFT 5
#define DA9055_BCORE_DEF_SHIFT 6
#define DA9055_BMEM_DEF_SHIFT 7
/* DA9055_REG_MON_REG_4 (addr=0x6D) */
#define DA9055_MON_A8_IDX_SHIFT 0
#define DA9055_MON_A89_IDX_MASK 0x3
#define DA9055_MON_A89_IDX_NONE 0x0
#define DA9055_MON_A89_IDX_BUCKCORE 0x1
#define DA9055_MON_A89_IDX_LDO3 0x2
#define DA9055_MON_A9_IDX_SHIFT 5
/* DA9055_REG_MON_REG_5 (addr=0x6E) */
#define DA9055_MON_A10_IDX_SHIFT 0
#define DA9055_MON_A10_IDX_MASK 0x3
#define DA9055_MON_A10_IDX_NONE 0x0
#define DA9055_MON_A10_IDX_LDO1 0x1
#define DA9055_MON_A10_IDX_LDO2 0x2
#define DA9055_MON_A10_IDX_LDO5 0x3
#define DA9055_MON_A10_IDX_LDO6 0x4
#endif /* __DA9055_REG_H */

52
include/linux/mfd/lp8788-isink.h Normal file
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@@ -0,0 +1,52 @@
/*
* TI LP8788 MFD - common definitions for current sinks
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ISINK_LP8788_H__
#define __ISINK_LP8788_H__
/* register address */
#define LP8788_ISINK_CTRL 0x99
#define LP8788_ISINK12_IOUT 0x9A
#define LP8788_ISINK3_IOUT 0x9B
#define LP8788_ISINK1_PWM 0x9C
#define LP8788_ISINK2_PWM 0x9D
#define LP8788_ISINK3_PWM 0x9E
/* mask bits */
#define LP8788_ISINK1_IOUT_M 0x0F /* Addr 9Ah */
#define LP8788_ISINK2_IOUT_M 0xF0
#define LP8788_ISINK3_IOUT_M 0x0F /* Addr 9Bh */
/* 6 bits used for PWM code : Addr 9C ~ 9Eh */
#define LP8788_ISINK_MAX_PWM 63
#define LP8788_ISINK_SCALE_OFFSET 3
static const u8 lp8788_iout_addr[] = {
LP8788_ISINK12_IOUT,
LP8788_ISINK12_IOUT,
LP8788_ISINK3_IOUT,
};
static const u8 lp8788_iout_mask[] = {
LP8788_ISINK1_IOUT_M,
LP8788_ISINK2_IOUT_M,
LP8788_ISINK3_IOUT_M,
};
static const u8 lp8788_pwm_addr[] = {
LP8788_ISINK1_PWM,
LP8788_ISINK2_PWM,
LP8788_ISINK3_PWM,
};
#endif

364
include/linux/mfd/lp8788.h Normal file
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@@ -0,0 +1,364 @@
/*
* TI LP8788 MFD Device
*
* Copyright 2012 Texas Instruments
*
* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __MFD_LP8788_H__
#define __MFD_LP8788_H__
#include <linux/gpio.h>
#include <linux/irqdomain.h>
#include <linux/regmap.h>
#define LP8788_DEV_BUCK "lp8788-buck"
#define LP8788_DEV_DLDO "lp8788-dldo"
#define LP8788_DEV_ALDO "lp8788-aldo"
#define LP8788_DEV_CHARGER "lp8788-charger"
#define LP8788_DEV_RTC "lp8788-rtc"
#define LP8788_DEV_BACKLIGHT "lp8788-backlight"
#define LP8788_DEV_VIBRATOR "lp8788-vibrator"
#define LP8788_DEV_KEYLED "lp8788-keyled"
#define LP8788_DEV_ADC "lp8788-adc"
#define LP8788_NUM_BUCKS 4
#define LP8788_NUM_DLDOS 12
#define LP8788_NUM_ALDOS 10
#define LP8788_NUM_BUCK2_DVS 2
#define LP8788_CHG_IRQ "CHG_IRQ"
#define LP8788_PRSW_IRQ "PRSW_IRQ"
#define LP8788_BATT_IRQ "BATT_IRQ"
#define LP8788_ALM_IRQ "ALARM_IRQ"
enum lp8788_int_id {
/* interrup register 1 : Addr 00h */
LP8788_INT_TSDL,
LP8788_INT_TSDH,
LP8788_INT_UVLO,
LP8788_INT_FLAGMON,
LP8788_INT_PWRON_TIME,
LP8788_INT_PWRON,
LP8788_INT_COMP1,
LP8788_INT_COMP2,
/* interrupt register 2 : Addr 01h */
LP8788_INT_CHG_INPUT_STATE,
LP8788_INT_CHG_STATE,
LP8788_INT_EOC,
LP8788_INT_CHG_RESTART,
LP8788_INT_RESTART_TIMEOUT,
LP8788_INT_FULLCHG_TIMEOUT,
LP8788_INT_PRECHG_TIMEOUT,
/* interrupt register 3 : Addr 02h */
LP8788_INT_RTC_ALARM1 = 17,
LP8788_INT_RTC_ALARM2,
LP8788_INT_ENTER_SYS_SUPPORT,
LP8788_INT_EXIT_SYS_SUPPORT,
LP8788_INT_BATT_LOW,
LP8788_INT_NO_BATT,
LP8788_INT_MAX = 24,
};
enum lp8788_dvs_sel {
DVS_SEL_V0,
DVS_SEL_V1,
DVS_SEL_V2,
DVS_SEL_V3,
};
enum lp8788_ext_ldo_en_id {
EN_ALDO1,
EN_ALDO234,
EN_ALDO5,
EN_ALDO7,
EN_DLDO7,
EN_DLDO911,
EN_LDOS_MAX,
};
enum lp8788_charger_event {
NO_CHARGER,
CHARGER_DETECTED,
};
enum lp8788_bl_ctrl_mode {
LP8788_BL_REGISTER_ONLY,
LP8788_BL_COMB_PWM_BASED, /* PWM + I2C, changed by PWM input */
LP8788_BL_COMB_REGISTER_BASED, /* PWM + I2C, changed by I2C */
};
enum lp8788_bl_dim_mode {
LP8788_DIM_EXPONENTIAL,
LP8788_DIM_LINEAR,
};
enum lp8788_bl_full_scale_current {
LP8788_FULLSCALE_5000uA,
LP8788_FULLSCALE_8500uA,
LP8788_FULLSCALE_1200uA,
LP8788_FULLSCALE_1550uA,
LP8788_FULLSCALE_1900uA,
LP8788_FULLSCALE_2250uA,
LP8788_FULLSCALE_2600uA,
LP8788_FULLSCALE_2950uA,
};
enum lp8788_bl_ramp_step {
LP8788_RAMP_8us,
LP8788_RAMP_1024us,
LP8788_RAMP_2048us,
LP8788_RAMP_4096us,
LP8788_RAMP_8192us,
LP8788_RAMP_16384us,
LP8788_RAMP_32768us,
LP8788_RAMP_65538us,
};
enum lp8788_bl_pwm_polarity {
LP8788_PWM_ACTIVE_HIGH,
LP8788_PWM_ACTIVE_LOW,
};
enum lp8788_isink_scale {
LP8788_ISINK_SCALE_100mA,
LP8788_ISINK_SCALE_120mA,
};
enum lp8788_isink_number {
LP8788_ISINK_1,
LP8788_ISINK_2,
LP8788_ISINK_3,
};
enum lp8788_alarm_sel {
LP8788_ALARM_1,
LP8788_ALARM_2,
LP8788_ALARM_MAX,
};
enum lp8788_adc_id {
LPADC_VBATT_5P5,
LPADC_VIN_CHG,
LPADC_IBATT,
LPADC_IC_TEMP,
LPADC_VBATT_6P0,
LPADC_VBATT_5P0,
LPADC_ADC1,
LPADC_ADC2,
LPADC_VDD,
LPADC_VCOIN,
LPADC_VDD_LDO,
LPADC_ADC3,
LPADC_ADC4,
LPADC_MAX,
};
struct lp8788;
/*
* lp8788_buck1_dvs
* @gpio : gpio pin number for dvs control
* @vsel : dvs selector for buck v1 register
*/
struct lp8788_buck1_dvs {
int gpio;
enum lp8788_dvs_sel vsel;
};
/*
* lp8788_buck2_dvs
* @gpio : two gpio pin numbers are used for dvs
* @vsel : dvs selector for buck v2 register
*/
struct lp8788_buck2_dvs {
int gpio[LP8788_NUM_BUCK2_DVS];
enum lp8788_dvs_sel vsel;
};
/*
* struct lp8788_ldo_enable_pin
*
* Basically, all LDOs are enabled through the I2C commands.
* But ALDO 1 ~ 5, 7, DLDO 7, 9, 11 can be enabled by external gpio pins.
*
* @gpio : gpio number which is used for enabling ldos
* @init_state : initial gpio state (ex. GPIOF_OUT_INIT_LOW)
*/
struct lp8788_ldo_enable_pin {
int gpio;
int init_state;
};
/*
* struct lp8788_chg_param
* @addr : charging control register address (range : 0x11 ~ 0x1C)
* @val : charging parameter value
*/
struct lp8788_chg_param {
u8 addr;
u8 val;
};
/*
* struct lp8788_charger_platform_data
* @vbatt_adc : adc selection id for battery voltage
* @batt_temp_adc : adc selection id for battery temperature
* @max_vbatt_mv : used for calculating battery capacity
* @chg_params : initial charging parameters
* @num_chg_params : numbers of charging parameters
* @charger_event : the charger event can be reported to the platform side
*/
struct lp8788_charger_platform_data {
enum lp8788_adc_id vbatt_adc;
enum lp8788_adc_id batt_temp_adc;
unsigned int max_vbatt_mv;
struct lp8788_chg_param *chg_params;
int num_chg_params;
void (*charger_event) (struct lp8788 *lp,
enum lp8788_charger_event event);
};
/*
* struct lp8788_bl_pwm_data
* @pwm_set_intensity : set duty of pwm
* @pwm_get_intensity : get current duty of pwm
*/
struct lp8788_bl_pwm_data {
void (*pwm_set_intensity) (int brightness, int max_brightness);
int (*pwm_get_intensity) (int max_brightness);
};
/*
* struct lp8788_backlight_platform_data
* @name : backlight driver name. (default: "lcd-backlight")
* @initial_brightness : initial value of backlight brightness
* @bl_mode : brightness control by pwm or lp8788 register
* @dim_mode : dimming mode selection
* @full_scale : full scale current setting
* @rise_time : brightness ramp up step time
* @fall_time : brightness ramp down step time
* @pwm_pol : pwm polarity setting when bl_mode is pwm based
* @pwm_data : platform specific pwm generation functions
* only valid when bl_mode is pwm based
*/
struct lp8788_backlight_platform_data {
char *name;
int initial_brightness;
enum lp8788_bl_ctrl_mode bl_mode;
enum lp8788_bl_dim_mode dim_mode;
enum lp8788_bl_full_scale_current full_scale;
enum lp8788_bl_ramp_step rise_time;
enum lp8788_bl_ramp_step fall_time;
enum lp8788_bl_pwm_polarity pwm_pol;
struct lp8788_bl_pwm_data pwm_data;
};
/*
* struct lp8788_led_platform_data
* @name : led driver name. (default: "keyboard-backlight")
* @scale : current scale
* @num : current sink number
* @iout_code : current output value (Addr 9Ah ~ 9Bh)
*/
struct lp8788_led_platform_data {
char *name;
enum lp8788_isink_scale scale;
enum lp8788_isink_number num;
int iout_code;
};
/*
* struct lp8788_vib_platform_data
* @name : vibrator driver name
* @scale : current scale
* @num : current sink number
* @iout_code : current output value (Addr 9Ah ~ 9Bh)
* @pwm_code : PWM code value (Addr 9Ch ~ 9Eh)
*/
struct lp8788_vib_platform_data {
char *name;
enum lp8788_isink_scale scale;
enum lp8788_isink_number num;
int iout_code;
int pwm_code;
};
/*
* struct lp8788_platform_data
* @init_func : used for initializing registers
* before mfd driver is registered
* @buck_data : regulator initial data for buck
* @dldo_data : regulator initial data for digital ldo
* @aldo_data : regulator initial data for analog ldo
* @buck1_dvs : gpio configurations for buck1 dvs
* @buck2_dvs : gpio configurations for buck2 dvs
* @ldo_pin : gpio configurations for enabling LDOs
* @chg_pdata : platform data for charger driver
* @alarm_sel : rtc alarm selection (1 or 2)
* @bl_pdata : configurable data for backlight driver
* @led_pdata : configurable data for led driver
* @vib_pdata : configurable data for vibrator driver
* @adc_pdata : iio map data for adc driver
*/
struct lp8788_platform_data {
/* general system information */
int (*init_func) (struct lp8788 *lp);
/* regulators */
struct regulator_init_data *buck_data[LP8788_NUM_BUCKS];
struct regulator_init_data *dldo_data[LP8788_NUM_DLDOS];
struct regulator_init_data *aldo_data[LP8788_NUM_ALDOS];
struct lp8788_buck1_dvs *buck1_dvs;
struct lp8788_buck2_dvs *buck2_dvs;
struct lp8788_ldo_enable_pin *ldo_pin[EN_LDOS_MAX];
/* charger */
struct lp8788_charger_platform_data *chg_pdata;
/* rtc alarm */
enum lp8788_alarm_sel alarm_sel;
/* backlight */
struct lp8788_backlight_platform_data *bl_pdata;
/* current sinks */
struct lp8788_led_platform_data *led_pdata;
struct lp8788_vib_platform_data *vib_pdata;
/* adc iio map data */
struct iio_map *adc_pdata;
};
/*
* struct lp8788
* @dev : parent device pointer
* @regmap : used for i2c communcation on accessing registers
* @irqdm : interrupt domain for handling nested interrupt
* @irq : pin number of IRQ_N
* @pdata : lp8788 platform specific data
*/
struct lp8788 {
struct device *dev;
struct regmap *regmap;
struct irq_domain *irqdm;
int irq;
struct lp8788_platform_data *pdata;
};
int lp8788_irq_init(struct lp8788 *lp, int chip_irq);
void lp8788_irq_exit(struct lp8788 *lp);
int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data);
int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count);
int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data);
int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data);
#endif

1
include/linux/mfd/lpc_ich.h
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@@ -43,6 +43,7 @@ struct lpc_ich_info {
char name[32];
unsigned int iTCO_version;
unsigned int gpio_version;
u8 use_gpio;
};
#endif

252
include/linux/mfd/max8907.h Normal file
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/*
* Functions to access MAX8907 power management chip.
*
* Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
* Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_MAX8907_H
#define __LINUX_MFD_MAX8907_H
#include <linux/mutex.h>
#include <linux/pm.h>
#define MAX8907_GEN_I2C_ADDR (0x78 >> 1)
#define MAX8907_ADC_I2C_ADDR (0x8e >> 1)
#define MAX8907_RTC_I2C_ADDR (0xd0 >> 1)
/* MAX8907 register map */
#define MAX8907_REG_SYSENSEL 0x00
#define MAX8907_REG_ON_OFF_IRQ1 0x01
#define MAX8907_REG_ON_OFF_IRQ1_MASK 0x02
#define MAX8907_REG_ON_OFF_STAT 0x03
#define MAX8907_REG_SDCTL1 0x04
#define MAX8907_REG_SDSEQCNT1 0x05
#define MAX8907_REG_SDV1 0x06
#define MAX8907_REG_SDCTL2 0x07
#define MAX8907_REG_SDSEQCNT2 0x08
#define MAX8907_REG_SDV2 0x09
#define MAX8907_REG_SDCTL3 0x0A
#define MAX8907_REG_SDSEQCNT3 0x0B
#define MAX8907_REG_SDV3 0x0C
#define MAX8907_REG_ON_OFF_IRQ2 0x0D
#define MAX8907_REG_ON_OFF_IRQ2_MASK 0x0E
#define MAX8907_REG_RESET_CNFG 0x0F
#define MAX8907_REG_LDOCTL16 0x10
#define MAX8907_REG_LDOSEQCNT16 0x11
#define MAX8907_REG_LDO16VOUT 0x12
#define MAX8907_REG_SDBYSEQCNT 0x13
#define MAX8907_REG_LDOCTL17 0x14
#define MAX8907_REG_LDOSEQCNT17 0x15
#define MAX8907_REG_LDO17VOUT 0x16
#define MAX8907_REG_LDOCTL1 0x18
#define MAX8907_REG_LDOSEQCNT1 0x19
#define MAX8907_REG_LDO1VOUT 0x1A
#define MAX8907_REG_LDOCTL2 0x1C
#define MAX8907_REG_LDOSEQCNT2 0x1D
#define MAX8907_REG_LDO2VOUT 0x1E
#define MAX8907_REG_LDOCTL3 0x20
#define MAX8907_REG_LDOSEQCNT3 0x21
#define MAX8907_REG_LDO3VOUT 0x22
#define MAX8907_REG_LDOCTL4 0x24
#define MAX8907_REG_LDOSEQCNT4 0x25
#define MAX8907_REG_LDO4VOUT 0x26
#define MAX8907_REG_LDOCTL5 0x28
#define MAX8907_REG_LDOSEQCNT5 0x29
#define MAX8907_REG_LDO5VOUT 0x2A
#define MAX8907_REG_LDOCTL6 0x2C
#define MAX8907_REG_LDOSEQCNT6 0x2D
#define MAX8907_REG_LDO6VOUT 0x2E
#define MAX8907_REG_LDOCTL7 0x30
#define MAX8907_REG_LDOSEQCNT7 0x31
#define MAX8907_REG_LDO7VOUT 0x32
#define MAX8907_REG_LDOCTL8 0x34
#define MAX8907_REG_LDOSEQCNT8 0x35
#define MAX8907_REG_LDO8VOUT 0x36
#define MAX8907_REG_LDOCTL9 0x38
#define MAX8907_REG_LDOSEQCNT9 0x39
#define MAX8907_REG_LDO9VOUT 0x3A
#define MAX8907_REG_LDOCTL10 0x3C
#define MAX8907_REG_LDOSEQCNT10 0x3D
#define MAX8907_REG_LDO10VOUT 0x3E
#define MAX8907_REG_LDOCTL11 0x40
#define MAX8907_REG_LDOSEQCNT11 0x41
#define MAX8907_REG_LDO11VOUT 0x42
#define MAX8907_REG_LDOCTL12 0x44
#define MAX8907_REG_LDOSEQCNT12 0x45
#define MAX8907_REG_LDO12VOUT 0x46
#define MAX8907_REG_LDOCTL13 0x48
#define MAX8907_REG_LDOSEQCNT13 0x49
#define MAX8907_REG_LDO13VOUT 0x4A
#define MAX8907_REG_LDOCTL14 0x4C
#define MAX8907_REG_LDOSEQCNT14 0x4D
#define MAX8907_REG_LDO14VOUT 0x4E
#define MAX8907_REG_LDOCTL15 0x50
#define MAX8907_REG_LDOSEQCNT15 0x51
#define MAX8907_REG_LDO15VOUT 0x52
#define MAX8907_REG_OUT5VEN 0x54
#define MAX8907_REG_OUT5VSEQ 0x55
#define MAX8907_REG_OUT33VEN 0x58
#define MAX8907_REG_OUT33VSEQ 0x59
#define MAX8907_REG_LDOCTL19 0x5C
#define MAX8907_REG_LDOSEQCNT19 0x5D
#define MAX8907_REG_LDO19VOUT 0x5E
#define MAX8907_REG_LBCNFG 0x60
#define MAX8907_REG_SEQ1CNFG 0x64
#define MAX8907_REG_SEQ2CNFG 0x65
#define MAX8907_REG_SEQ3CNFG 0x66
#define MAX8907_REG_SEQ4CNFG 0x67
#define MAX8907_REG_SEQ5CNFG 0x68
#define MAX8907_REG_SEQ6CNFG 0x69
#define MAX8907_REG_SEQ7CNFG 0x6A
#define MAX8907_REG_LDOCTL18 0x72
#define MAX8907_REG_LDOSEQCNT18 0x73
#define MAX8907_REG_LDO18VOUT 0x74
#define MAX8907_REG_BBAT_CNFG 0x78
#define MAX8907_REG_CHG_CNTL1 0x7C
#define MAX8907_REG_CHG_CNTL2 0x7D
#define MAX8907_REG_CHG_IRQ1 0x7E
#define MAX8907_REG_CHG_IRQ2 0x7F
#define MAX8907_REG_CHG_IRQ1_MASK 0x80
#define MAX8907_REG_CHG_IRQ2_MASK 0x81
#define MAX8907_REG_CHG_STAT 0x82
#define MAX8907_REG_WLED_MODE_CNTL 0x84
#define MAX8907_REG_ILED_CNTL 0x84
#define MAX8907_REG_II1RR 0x8E
#define MAX8907_REG_II2RR 0x8F
#define MAX8907_REG_LDOCTL20 0x9C
#define MAX8907_REG_LDOSEQCNT20 0x9D
#define MAX8907_REG_LDO20VOUT 0x9E
/* RTC register map */
#define MAX8907_REG_RTC_SEC 0x00
#define MAX8907_REG_RTC_MIN 0x01
#define MAX8907_REG_RTC_HOURS 0x02
#define MAX8907_REG_RTC_WEEKDAY 0x03
#define MAX8907_REG_RTC_DATE 0x04
#define MAX8907_REG_RTC_MONTH 0x05
#define MAX8907_REG_RTC_YEAR1 0x06
#define MAX8907_REG_RTC_YEAR2 0x07
#define MAX8907_REG_ALARM0_SEC 0x08
#define MAX8907_REG_ALARM0_MIN 0x09
#define MAX8907_REG_ALARM0_HOURS 0x0A
#define MAX8907_REG_ALARM0_WEEKDAY 0x0B
#define MAX8907_REG_ALARM0_DATE 0x0C
#define MAX8907_REG_ALARM0_MONTH 0x0D
#define MAX8907_REG_ALARM0_YEAR1 0x0E
#define MAX8907_REG_ALARM0_YEAR2 0x0F
#define MAX8907_REG_ALARM1_SEC 0x10
#define MAX8907_REG_ALARM1_MIN 0x11
#define MAX8907_REG_ALARM1_HOURS 0x12
#define MAX8907_REG_ALARM1_WEEKDAY 0x13
#define MAX8907_REG_ALARM1_DATE 0x14
#define MAX8907_REG_ALARM1_MONTH 0x15
#define MAX8907_REG_ALARM1_YEAR1 0x16
#define MAX8907_REG_ALARM1_YEAR2 0x17
#define MAX8907_REG_ALARM0_CNTL 0x18
#define MAX8907_REG_ALARM1_CNTL 0x19
#define MAX8907_REG_RTC_STATUS 0x1A
#define MAX8907_REG_RTC_CNTL 0x1B
#define MAX8907_REG_RTC_IRQ 0x1C
#define MAX8907_REG_RTC_IRQ_MASK 0x1D
#define MAX8907_REG_MPL_CNTL 0x1E
/* ADC and Touch Screen Controller register map */
#define MAX8907_CTL 0
#define MAX8907_SEQCNT 1
#define MAX8907_VOUT 2
/* mask bit fields */
#define MAX8907_MASK_LDO_SEQ 0x1C
#define MAX8907_MASK_LDO_EN 0x01
#define MAX8907_MASK_VBBATTCV 0x03
#define MAX8907_MASK_OUT5V_VINEN 0x10
#define MAX8907_MASK_OUT5V_ENSRC 0x0E
#define MAX8907_MASK_OUT5V_EN 0x01
#define MAX8907_MASK_POWER_OFF 0x40
/* Regulator IDs */
#define MAX8907_MBATT 0
#define MAX8907_SD1 1
#define MAX8907_SD2 2
#define MAX8907_SD3 3
#define MAX8907_LDO1 4
#define MAX8907_LDO2 5
#define MAX8907_LDO3 6
#define MAX8907_LDO4 7
#define MAX8907_LDO5 8
#define MAX8907_LDO6 9
#define MAX8907_LDO7 10
#define MAX8907_LDO8 11
#define MAX8907_LDO9 12
#define MAX8907_LDO10 13
#define MAX8907_LDO11 14
#define MAX8907_LDO12 15
#define MAX8907_LDO13 16
#define MAX8907_LDO14 17
#define MAX8907_LDO15 18
#define MAX8907_LDO16 19
#define MAX8907_LDO17 20
#define MAX8907_LDO18 21
#define MAX8907_LDO19 22
#define MAX8907_LDO20 23
#define MAX8907_OUT5V 24
#define MAX8907_OUT33V 25
#define MAX8907_BBAT 26
#define MAX8907_SDBY 27
#define MAX8907_VRTC 28
#define MAX8907_NUM_REGULATORS (MAX8907_VRTC + 1)
/* IRQ definitions */
enum {
MAX8907_IRQ_VCHG_DC_OVP = 0,
MAX8907_IRQ_VCHG_DC_F,
MAX8907_IRQ_VCHG_DC_R,
MAX8907_IRQ_VCHG_THM_OK_R,
MAX8907_IRQ_VCHG_THM_OK_F,
MAX8907_IRQ_VCHG_MBATTLOW_F,
MAX8907_IRQ_VCHG_MBATTLOW_R,
MAX8907_IRQ_VCHG_RST,
MAX8907_IRQ_VCHG_DONE,
MAX8907_IRQ_VCHG_TOPOFF,
MAX8907_IRQ_VCHG_TMR_FAULT,
MAX8907_IRQ_GPM_RSTIN = 0,
MAX8907_IRQ_GPM_MPL,
MAX8907_IRQ_GPM_SW_3SEC,
MAX8907_IRQ_GPM_EXTON_F,
MAX8907_IRQ_GPM_EXTON_R,
MAX8907_IRQ_GPM_SW_1SEC,
MAX8907_IRQ_GPM_SW_F,
MAX8907_IRQ_GPM_SW_R,
MAX8907_IRQ_GPM_SYSCKEN_F,
MAX8907_IRQ_GPM_SYSCKEN_R,
MAX8907_IRQ_RTC_ALARM1 = 0,
MAX8907_IRQ_RTC_ALARM0,
};
struct max8907_platform_data {
struct regulator_init_data *init_data[MAX8907_NUM_REGULATORS];
bool pm_off;
};
struct regmap_irq_chips_data;
struct max8907 {
struct device *dev;
struct mutex irq_lock;
struct i2c_client *i2c_gen;
struct i2c_client *i2c_rtc;
struct regmap *regmap_gen;
struct regmap *regmap_rtc;
struct regmap_irq_chip_data *irqc_chg;
struct regmap_irq_chip_data *irqc_on_off;
struct regmap_irq_chip_data *irqc_rtc;
};
#endif

26
include/linux/mfd/max8925.h
View File

@@ -158,8 +158,6 @@ enum {
#define TSC_IRQ_MASK (0x03)
#define RTC_IRQ_MASK (0x0c)
#define MAX8925_MAX_REGULATOR (23)
#define MAX8925_NAME_SIZE (32)
/* IRQ definitions */
@@ -236,7 +234,29 @@ struct max8925_platform_data {
struct max8925_backlight_pdata *backlight;
struct max8925_touch_pdata *touch;
struct max8925_power_pdata *power;
struct regulator_init_data *regulator[MAX8925_MAX_REGULATOR];
struct regulator_init_data *sd1;
struct regulator_init_data *sd2;
struct regulator_init_data *sd3;
struct regulator_init_data *ldo1;
struct regulator_init_data *ldo2;
struct regulator_init_data *ldo3;
struct regulator_init_data *ldo4;
struct regulator_init_data *ldo5;
struct regulator_init_data *ldo6;
struct regulator_init_data *ldo7;
struct regulator_init_data *ldo8;
struct regulator_init_data *ldo9;
struct regulator_init_data *ldo10;
struct regulator_init_data *ldo11;
struct regulator_init_data *ldo12;
struct regulator_init_data *ldo13;
struct regulator_init_data *ldo14;
struct regulator_init_data *ldo15;
struct regulator_init_data *ldo16;
struct regulator_init_data *ldo17;
struct regulator_init_data *ldo18;
struct regulator_init_data *ldo19;
struct regulator_init_data *ldo20;
int irq_base;
int tsc_irq;

232
include/linux/mfd/palmas.h
View File

@@ -23,6 +23,9 @@
#define PALMAS_NUM_CLIENTS 3
struct palmas_pmic;
struct palmas_gpadc;
struct palmas_resource;
struct palmas_usb;
struct palmas {
struct device *dev;
@@ -41,6 +44,9 @@ struct palmas {
/* Child Devices */
struct palmas_pmic *pmic;
struct palmas_gpadc *gpadc;
struct palmas_resource *resource;
struct palmas_usb *usb;
/* GPIO MUXing */
u8 gpio_muxed;
@@ -48,6 +54,23 @@ struct palmas {
u8 pwm_muxed;
};
struct palmas_gpadc_platform_data {
/* Channel 3 current source is only enabled during conversion */
int ch3_current;
/* Channel 0 current source can be used for battery detection.
* If used for battery detection this will cause a permanent current
* consumption depending on current level set here.
*/
int ch0_current;
/* default BAT_REMOVAL_DAT setting on device probe */
int bat_removal;
/* Sets the START_POLARITY bit in the RT_CTRL register */
int start_polarity;
};
struct palmas_reg_init {
/* warm_rest controls the voltage levels after a warm reset
*
@@ -107,21 +130,94 @@ struct palmas_reg_init {
};
enum palmas_regulators {
/* SMPS regulators */
PALMAS_REG_SMPS12,
PALMAS_REG_SMPS123,
PALMAS_REG_SMPS3,
PALMAS_REG_SMPS45,
PALMAS_REG_SMPS457,
PALMAS_REG_SMPS6,
PALMAS_REG_SMPS7,
PALMAS_REG_SMPS8,
PALMAS_REG_SMPS9,
PALMAS_REG_SMPS10,
/* LDO regulators */
PALMAS_REG_LDO1,
PALMAS_REG_LDO2,
PALMAS_REG_LDO3,
PALMAS_REG_LDO4,
PALMAS_REG_LDO5,
PALMAS_REG_LDO6,
PALMAS_REG_LDO7,
PALMAS_REG_LDO8,
PALMAS_REG_LDO9,
PALMAS_REG_LDOLN,
PALMAS_REG_LDOUSB,
/* Total number of regulators */
PALMAS_NUM_REGS,
};
struct palmas_pmic_platform_data {
/* An array of pointers to regulator init data indexed by regulator
* ID
*/
struct regulator_init_data **reg_data;
struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
/* An array of pointers to structures containing sleep mode and DVS
* configuration for regulators indexed by ID
*/
struct palmas_reg_init **reg_init;
struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
/* use LDO6 for vibrator control */
int ldo6_vibrator;
};
struct palmas_usb_platform_data {
/* Set this if platform wishes its own vbus control */
int no_control_vbus;
/* Do we enable the wakeup comparator on probe */
int wakeup;
};
struct palmas_resource_platform_data {
int regen1_mode_sleep;
int regen2_mode_sleep;
int sysen1_mode_sleep;
int sysen2_mode_sleep;
/* bitfield to be loaded to NSLEEP_RES_ASSIGN */
u8 nsleep_res;
/* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
u8 nsleep_smps;
/* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
u8 nsleep_ldo1;
/* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
u8 nsleep_ldo2;
/* bitfield to be loaded to ENABLE1_RES_ASSIGN */
u8 enable1_res;
/* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
u8 enable1_smps;
/* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
u8 enable1_ldo1;
/* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
u8 enable1_ldo2;
/* bitfield to be loaded to ENABLE2_RES_ASSIGN */
u8 enable2_res;
/* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
u8 enable2_smps;
/* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
u8 enable2_ldo1;
/* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
u8 enable2_ldo2;
};
struct palmas_clk_platform_data {
int clk32kg_mode_sleep;
int clk32kgaudio_mode_sleep;
};
struct palmas_platform_data {
@@ -138,8 +234,49 @@ struct palmas_platform_data {
u8 pad1, pad2;
struct palmas_pmic_platform_data *pmic_pdata;
struct palmas_gpadc_platform_data *gpadc_pdata;
struct palmas_usb_platform_data *usb_pdata;
struct palmas_resource_platform_data *resource_pdata;
struct palmas_clk_platform_data *clk_pdata;
};
struct palmas_gpadc_calibration {
s32 gain;
s32 gain_error;
s32 offset_error;
};
struct palmas_gpadc {
struct device *dev;
struct palmas *palmas;
int ch3_current;
int ch0_current;
int gpadc_force;
int bat_removal;
struct mutex reading_lock;
struct completion irq_complete;
int eoc_sw_irq;
struct palmas_gpadc_calibration *palmas_cal_tbl;
int conv0_channel;
int conv1_channel;
int rt_channel;
};
struct palmas_gpadc_result {
s32 raw_code;
s32 corrected_code;
s32 result;
};
#define PALMAS_MAX_CHANNELS 16
/* Define the palmas IRQ numbers */
enum palmas_irqs {
/* INT1 registers */
@@ -182,34 +319,6 @@ enum palmas_irqs {
PALMAS_NUM_IRQ,
};
enum palmas_regulators {
/* SMPS regulators */
PALMAS_REG_SMPS12,
PALMAS_REG_SMPS123,
PALMAS_REG_SMPS3,
PALMAS_REG_SMPS45,
PALMAS_REG_SMPS457,
PALMAS_REG_SMPS6,
PALMAS_REG_SMPS7,
PALMAS_REG_SMPS8,
PALMAS_REG_SMPS9,
PALMAS_REG_SMPS10,
/* LDO regulators */
PALMAS_REG_LDO1,
PALMAS_REG_LDO2,
PALMAS_REG_LDO3,
PALMAS_REG_LDO4,
PALMAS_REG_LDO5,
PALMAS_REG_LDO6,
PALMAS_REG_LDO7,
PALMAS_REG_LDO8,
PALMAS_REG_LDO9,
PALMAS_REG_LDOLN,
PALMAS_REG_LDOUSB,
/* Total number of regulators */
PALMAS_NUM_REGS,
};
struct palmas_pmic {
struct palmas *palmas;
struct device *dev;
@@ -223,6 +332,69 @@ struct palmas_pmic {
int range[PALMAS_REG_SMPS10];
};
struct palmas_resource {
struct palmas *palmas;
struct device *dev;
};
struct palmas_usb {
struct palmas *palmas;
struct device *dev;
/* for vbus reporting with irqs disabled */
spinlock_t lock;
struct regulator *vbus_reg;
/* used to set vbus, in atomic path */
struct work_struct set_vbus_work;
int irq1;
int irq2;
int irq3;
int irq4;
int vbus_enable;
u8 linkstat;
};
#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
enum usb_irq_events {
/* Wakeup events from INT3 */
PALMAS_USB_ID_WAKEPUP,
PALMAS_USB_VBUS_WAKEUP,
/* ID_OTG_EVENTS */
PALMAS_USB_ID_GND,
N_PALMAS_USB_ID_GND,
PALMAS_USB_ID_C,
N_PALMAS_USB_ID_C,
PALMAS_USB_ID_B,
N_PALMAS_USB_ID_B,
PALMAS_USB_ID_A,
N_PALMAS_USB_ID_A,
PALMAS_USB_ID_FLOAT,
N_PALMAS_USB_ID_FLOAT,
/* VBUS_OTG_EVENTS */
PALMAS_USB_VB_SESS_END,
N_PALMAS_USB_VB_SESS_END,
PALMAS_USB_VB_SESS_VLD,
N_PALMAS_USB_VB_SESS_VLD,
PALMAS_USB_VA_SESS_VLD,
N_PALMAS_USB_VA_SESS_VLD,
PALMAS_USB_VA_VBUS_VLD,
N_PALMAS_USB_VA_VBUS_VLD,
PALMAS_USB_VADP_SNS,
N_PALMAS_USB_VADP_SNS,
PALMAS_USB_VADP_PRB,
N_PALMAS_USB_VADP_PRB,
PALMAS_USB_VOTG_SESS_VLD,
N_PALMAS_USB_VOTG_SESS_VLD,
};
/* defines so we can store the mux settings */
#define PALMAS_GPIO_0_MUXED (1 << 0)
#define PALMAS_GPIO_1_MUXED (1 << 1)

109
include/linux/mfd/smsc.h Normal file
View File

@@ -0,0 +1,109 @@
/*
* SMSC ECE1099
*
* Copyright 2012 Texas Instruments Inc.
*
* Author: Sourav Poddar <sourav.poddar@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SMSC_H
#define __LINUX_MFD_SMSC_H
#include <linux/regmap.h>
#define SMSC_ID_ECE1099 1
#define SMSC_NUM_CLIENTS 2
#define SMSC_BASE_ADDR 0x38
#define OMAP_GPIO_SMSC_IRQ 151
#define SMSC_MAXGPIO 32
#define SMSC_BANK(offs) ((offs) >> 3)
#define SMSC_BIT(offs) (1u << ((offs) & 0x7))
struct smsc {
struct device *dev;
struct i2c_client *i2c_clients[SMSC_NUM_CLIENTS];
struct regmap *regmap;
int clk;
/* Stored chip id */
int id;
};
struct smsc_gpio;
struct smsc_keypad;
static inline int smsc_read(struct device *child, unsigned int reg,
unsigned int *dest)
{
struct smsc *smsc = dev_get_drvdata(child->parent);
return regmap_read(smsc->regmap, reg, dest);
}
static inline int smsc_write(struct device *child, unsigned int reg,
unsigned int value)
{
struct smsc *smsc = dev_get_drvdata(child->parent);
return regmap_write(smsc->regmap, reg, value);
}
/* Registers for SMSC */
#define SMSC_RESET 0xF5
#define SMSC_GRP_INT 0xF9
#define SMSC_CLK_CTRL 0xFA
#define SMSC_WKUP_CTRL 0xFB
#define SMSC_DEV_ID 0xFC
#define SMSC_DEV_REV 0xFD
#define SMSC_VEN_ID_L 0xFE
#define SMSC_VEN_ID_H 0xFF
/* CLK VALUE */
#define SMSC_CLK_VALUE 0x13
/* Registers for function GPIO INPUT */
#define SMSC_GPIO_DATA_IN_START 0x00
/* Registers for function GPIO OUPUT */
#define SMSC_GPIO_DATA_OUT_START 0x05
/* Definitions for SMSC GPIO CONFIGURATION REGISTER*/
#define SMSC_GPIO_INPUT_LOW 0x01
#define SMSC_GPIO_INPUT_RISING 0x09
#define SMSC_GPIO_INPUT_FALLING 0x11
#define SMSC_GPIO_INPUT_BOTH_EDGE 0x19
#define SMSC_GPIO_OUTPUT_PP 0x21
#define SMSC_GPIO_OUTPUT_OP 0x31
#define GRP_INT_STAT 0xf9
#define SMSC_GPI_INT 0x0f
#define SMSC_CFG_START 0x0A
/* Registers for SMSC GPIO INTERRUPT STATUS REGISTER*/
#define SMSC_GPIO_INT_STAT_START 0x32
/* Registers for SMSC GPIO INTERRUPT MASK REGISTER*/
#define SMSC_GPIO_INT_MASK_START 0x37
/* Registers for SMSC function KEYPAD*/
#define SMSC_KP_OUT 0x40
#define SMSC_KP_IN 0x41
#define SMSC_KP_INT_STAT 0x42
#define SMSC_KP_INT_MASK 0x43
/* Definitions for keypad */
#define SMSC_KP_KSO 0x70
#define SMSC_KP_KSI 0x51
#define SMSC_KSO_ALL_LOW 0x20
#define SMSC_KP_SET_LOW_PWR 0x0B
#define SMSC_KP_SET_HIGH 0xFF
#define SMSC_KSO_EVAL 0x00
#endif /* __LINUX_MFD_SMSC_H */

23
include/linux/mfd/syscon.h Normal file
View File

@@ -0,0 +1,23 @@
/*
* System Control Driver
*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __LINUX_MFD_SYSCON_H__
#define __LINUX_MFD_SYSCON_H__
extern struct regmap *syscon_node_to_regmap(struct device_node *np);
extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
extern struct regmap *syscon_regmap_lookup_by_phandle(
struct device_node *np,
const char *property);
#endif /* __LINUX_MFD_SYSCON_H__ */

319
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h Normal file
View File

@@ -0,0 +1,319 @@
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
#define __LINUX_IMX6Q_IOMUXC_GPR_H
#include <linux/bitops.h>
#define IOMUXC_GPR0 0x00
#define IOMUXC_GPR1 0x04
#define IOMUXC_GPR2 0x08
#define IOMUXC_GPR3 0x0c
#define IOMUXC_GPR4 0x10
#define IOMUXC_GPR5 0x14
#define IOMUXC_GPR6 0x18
#define IOMUXC_GPR7 0x1c
#define IOMUXC_GPR8 0x20
#define IOMUXC_GPR9 0x24
#define IOMUXC_GPR10 0x28
#define IOMUXC_GPR11 0x2c
#define IOMUXC_GPR12 0x30
#define IOMUXC_GPR13 0x34
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x0 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30)
#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0x0 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28)
#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0x0 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26)
#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK (0x3 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0x0 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22)
#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (0x3 << 22)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK (0x3 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0x0 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14)
#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0)
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1 0x0
#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0)
#define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30)
#define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28)
#define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27)
#define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26)
#define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25)
#define IMX6Q_GPR1_DPI_OFF BIT(24)
#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
#define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16)
#define IMX6Q_GPR1_USB_EXP_MODE BIT(15)
#define IMX6Q_GPR1_PCIE_INT BIT(14)
#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
#define IMX6Q_GPR1_GINT BIT(12)
#define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
#define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
#define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
#define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10)
#define IMX6Q_GPR1_ACT_CS3 BIT(9)
#define IMX6Q_GPR1_ADDRS2_MASK (0x3 << 7)
#define IMX6Q_GPR1_ACT_CS2 BIT(6)
#define IMX6Q_GPR1_ADDRS1_MASK (0x3 << 4)
#define IMX6Q_GPR1_ACT_CS1 BIT(3)
#define IMX6Q_GPR1_ADDRS0_MASK (0x3 << 1)
#define IMX6Q_GPR1_ACT_CS0 BIT(0)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK (0x3 << 20)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_5 (0x0 << 20)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 20)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20)
#define IMX6Q_GPR2_COUNTER_RESET_VAL_6 (0x3 << 20)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK (0x7 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0 (0x0 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1 (0x1 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3 (0x3 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4 (0x4 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5 (0x5 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6 (0x6 << 16)
#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7 (0x7 << 16)
#define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15)
#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR 0x0
#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15)
#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10)
#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H 0x0
#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10)
#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9)
#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H 0x0
#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9)
#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8)
#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG 0x0
#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8)
#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7)
#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT 0x0
#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7)
#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6)
#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG 0x0
#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6)
#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5)
#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT 0x0
#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5)
#define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4)
#define IMX6Q_GPR2_CH1_MODE_MASK (0x3 << 2)
#define IMX6Q_GPR2_CH1_MODE_DISABLE (0x0 << 2)
#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0 (0x1 << 2)
#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1 (0x3 << 2)
#define IMX6Q_GPR2_CH0_MODE_MASK (0x3 << 0)
#define IMX6Q_GPR2_CH0_MODE_DISABLE (0x0 << 0)
#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0 (0x1 << 0)
#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1 (0x3 << 0)
#define IMX6Q_GPR3_GPU_DBG_MASK (0x3 << 29)
#define IMX6Q_GPR3_GPU_DBG_GPU3D (0x0 << 29)
#define IMX6Q_GPR3_GPU_DBG_GPU2D (0x1 << 29)
#define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29)
#define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28)
#define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27)
#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26)
#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25)
#define IMX6Q_GPR3_OCRAM_CTL_MASK (0xf << 21)
#define IMX6Q_GPR3_OCRAM_STATUS_MASK (0xf << 17)
#define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16)
#define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15)
#define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14)
#define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13)
#define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12)
#define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11)
#define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8)
#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1 (0x3 << 8)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6)
#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4)
#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4)
#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2)
#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2)
#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2)
#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2)
#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1 (0x3 << 2)
#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31)
#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30)
#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29)
#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28)
#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27)
#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26)
#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25)
#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24)
#define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19)
#define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18)
#define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17)
#define IMX6Q_GPR4_ENET_STOP_ACK BIT(16)
#define IMX6Q_GPR4_SOC_VERSION_MASK (0xff << 8)
#define IMX6Q_GPR4_SOC_VERSION_OFF 0x8
#define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7)
#define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6)
#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3)
#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2)
#define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1)
#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
#define IMX6Q_GPR10_LOCK_DBG_EN BIT(29)
#define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28)
#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27)
#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR (0x3f << 21)
#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20)
#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK (0x3 << 18)
#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK (0x3 << 16)
#define IMX6Q_GPR10_DBG_EN BIT(13)
#define IMX6Q_GPR10_DBG_CLK_EN BIT(12)
#define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11)
#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY 0x0
#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11)
#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5)
#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2)
#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0)
#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0)
#define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27)
#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */

1
include/linux/mfd/tc3589x.h
View File

@@ -117,6 +117,7 @@ struct tc3589x {
struct mutex lock;
struct device *dev;
struct i2c_client *i2c;
struct irq_domain *domain;
int irq_base;
int num_gpio;

18
include/linux/mfd/tps65217.h
View File

@@ -213,6 +213,23 @@ enum tps65217_regulator_id {
/* Number of total regulators available */
#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
enum tps65217_bl_isel {
TPS65217_BL_ISET1 = 1,
TPS65217_BL_ISET2,
};
enum tps65217_bl_fdim {
TPS65217_BL_FDIM_100HZ,
TPS65217_BL_FDIM_200HZ,
TPS65217_BL_FDIM_500HZ,
TPS65217_BL_FDIM_1000HZ,
};
struct tps65217_bl_pdata {
enum tps65217_bl_isel isel;
enum tps65217_bl_fdim fdim;
};
/**
* struct tps65217_board - packages regulator init data
* @tps65217_regulator_data: regulator initialization values
@@ -222,6 +239,7 @@ enum tps65217_regulator_id {
struct tps65217_board {
struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
struct device_node *of_node[TPS65217_NUM_REGULATOR];
struct tps65217_bl_pdata *bl_pdata;
};
/**

1
include/linux/mfd/tps6586x.h
View File

@@ -78,6 +78,7 @@ struct tps6586x_platform_data {
int gpio_base;
int irq_base;
bool pm_off;
};
/*

3
include/linux/mfd/tps65910.h
View File

@@ -366,6 +366,8 @@
/*Register DEVCTRL (0x80) register.RegisterDescription */
#define DEVCTRL_PWR_OFF_MASK 0x80
#define DEVCTRL_PWR_OFF_SHIFT 7
#define DEVCTRL_RTC_PWDN_MASK 0x40
#define DEVCTRL_RTC_PWDN_SHIFT 6
#define DEVCTRL_CK32K_CTRL_MASK 0x20
@@ -809,6 +811,7 @@ struct tps65910_board {
int vmbch2_threshold;
bool en_ck32k_xtal;
bool en_dev_slp;
bool pm_off;
struct tps65910_sleep_keepon_data *slp_keepon;
bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];

11
include/linux/mfd/twl6040.h
View File

@@ -143,7 +143,7 @@
#define TWL6040_GPO1 0x01
#define TWL6040_GPO2 0x02
#define TWL6040_GPO3 0x03
#define TWL6040_GPO3 0x04
/* ACCCTL (0x2D) fields */
@@ -158,7 +158,7 @@
#define TWL6040_VIBROCDET 0x20
#define TWL6040_TSHUTDET 0x40
#define TWL6040_CELLS 2
#define TWL6040_CELLS 3
#define TWL6040_REV_ES1_0 0x00
#define TWL6040_REV_ES1_1 0x01 /* Rev ES1.1 and ES1.2 */
@@ -176,6 +176,8 @@
#define TWL6040_SYSCLK_SEL_LPPLL 0
#define TWL6040_SYSCLK_SEL_HPPLL 1
#define TWL6040_GPO_MAX 3
struct twl6040_codec_data {
u16 hs_left_step;
u16 hs_right_step;
@@ -192,11 +194,16 @@ struct twl6040_vibra_data {
int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */
};
struct twl6040_gpo_data {
int gpio_base;
};
struct twl6040_platform_data {
int audpwron_gpio; /* audio power-on gpio */
struct twl6040_codec_data *codec;
struct twl6040_vibra_data *vibra;
struct twl6040_gpo_data *gpo;
};
struct regmap;