Merge tag 'drm-next-2019-09-18' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "This is the main pull request for 5.4-rc1 merge window. I don't think there is anything outstanding so next week should just be fixes, but we'll see if I missed anything. I landed some fixes earlier in the week but got delayed writing summary and sending it out, due to a mix of sick kid and jetlag! There are some fixes pending, but I'd rather get the main merge out of the way instead of delaying it longer. It's also pretty large in commit count and new amd header file size. The largest thing is four new amdgpu products (navi12/14, arcturus and renoir APU support). Otherwise it's pretty much lots of work across the board, i915 has started landing tigerlake support, lots of icelake fixes and lots of locking reworking for future gpu support, lots of header file rework (drmP.h is nearly gone), some old legacy hacks (DRM_WAIT_ON) have been put into the places they are needed. uapi: - content protection type property for HDCP core: - rework include dependencies - lots of drmP.h removals - link rate calculation robustness fix - make fb helper map only when required - add connector->DDC adapter link - DRM_WAIT_ON removed - drop DRM_AUTH usage from drivers dma-buf: - reservation object fence helper dma-fence: - shrink dma_fence struct - merge signal functions - store timestamps in dma_fence - selftests ttm: - embed drm_get_object struct into ttm_buffer_object - release_notify callback bridges: - sii902x - audio graph card support - tc358767 - aux data handling rework - ti-snd64dsi86 - debugfs support, DSI mode flags support panels: - Support for GiantPlus GPM940B0, Sharp LQ070Y3DG3B, Ortustech COM37H3M, Novatek NT39016, Sharp LS020B1DD01D, Raydium RM67191, Boe Himax8279d, Sharp LD-D5116Z01B - TI nspire, NEC NL8048HL11, LG Philips LB035Q02, Sharp LS037V7DW01, Sony ACX565AKM, Toppoly TD028TTEC1 Toppoly TD043MTEA1 i915: - Initial tigerlake platform support - Locking simplification work, general all over refactoring. - Selftests - HDCP debug info improvements - DSI properties - Icelake display PLL fixes, colorspace fixes, bandwidth fixes, DSI suspend/resume - GuC fixes - Perf fixes - ElkhartLake enablement - DP MST fixes - GVT - command parser enhancements amdgpu: - add wipe memory on release flag for buffer creation - Navi12/14 support (may be marked experimental) - Arcturus support - Renoir APU support - mclk DPM for Navi - DC display fixes - Raven scatter/gather support - RAS support for GFX - Navi12 + Arcturus power features - GPU reset for Picasso - smu11 i2c controller support amdkfd: - navi12/14 support - Arcturus support radeon: - kexec fix nouveau: - improved display color management - detect lack of GPU power cables vmwgfx: - evicition priority support - remove unused security feature msm: - msm8998 display support - better async commit support for cursor updates etnaviv: - per-process address space support - performance counter fixes - softpin support mcde: - DCS transfers fix exynos: - drmP.h cleanup lima: - reduce logging kirin: - misc clenaups komeda: - dual-link support - DT memory regions hisilicon: - misc fixes imx: - IPUv3 image converter fixes - 32-bit RGB V4L2 pixel format support ingenic: - more support for panel related cases mgag200: - cursor support fix panfrost: - export GPU features register to userspace - gpu heap allocations - per-fd address space support pl111: - CLD pads wiring support removed from DT rockchip: - rework to use DRM PSR helpers - fix bug in VOP_WIN_GET macro - DSI DT binding rework sun4i: - improve support for color encoding and range - DDC enabled GPIO tinydrm: - rework SPI support - improve MIPI-DBI support - moved to drm/tiny vkms: - rework CRC tracking dw-hdmi: - get_eld and i2s improvements gm12u320: - misc fixes meson: - global code cleanup - vpu feature detect omap: - alpha/pixel blend mode properties rcar-du: - misc fixes" * tag 'drm-next-2019-09-18' of git://anongit.freedesktop.org/drm/drm: (2112 commits) drm/nouveau/bar/gm20b: Avoid BAR1 teardown during init drm/nouveau: Fix ordering between TTM and GEM release drm/nouveau/prime: Extend DMA reservation object lock drm/nouveau: Fix fallout from reservation object rework drm/nouveau/kms/nv50-: Don't create MSTMs for eDP connectors drm/i915: Use NOEVICT for first pass on attemping to pin a GGTT mmap drm/i915: to make vgpu ppgtt notificaiton as atomic operation drm/i915: Flush the existing fence before GGTT read/write drm/i915: Hold irq-off for the entire fake lock period drm/i915/gvt: update RING_START reg of vGPU when the context is submitted to i915 drm/i915/gvt: update vgpu workload head pointer correctly drm/mcde: Fix DSI transfers drm/msm: Use the correct dma_sync calls harder drm/msm: remove unlikely() from WARN_ON() conditions drm/msm/dsi: Fix return value check for clk_get_parent drm/msm: add atomic traces drm/msm/dpu: async commit support drm/msm: async commit support drm/msm: split power control from prepare/complete_commit drm/msm: add kms->flush_commit() ...
This commit is contained in:
@@ -39,14 +39,6 @@ static int fb_notifier_callback(struct notifier_block *self,
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if (event == FB_EVENT_BLANK) {
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if (ld->ops->set_power)
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ld->ops->set_power(ld, *(int *)evdata->data);
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} else if (event == FB_EARLY_EVENT_BLANK) {
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if (ld->ops->early_set_power)
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ld->ops->early_set_power(ld,
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*(int *)evdata->data);
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} else if (event == FB_R_EARLY_EVENT_BLANK) {
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if (ld->ops->r_early_set_power)
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ld->ops->r_early_set_power(ld,
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*(int *)evdata->data);
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} else {
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if (ld->ops->set_mode)
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ld->ops->set_mode(ld, evdata->data);
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@@ -561,8 +561,10 @@ static int clcdfb_of_get_dpi_panel_mode(struct device_node *node,
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struct videomode video;
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err = of_get_display_timing(node, "panel-timing", &timing);
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if (err)
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if (err) {
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pr_err("%pOF: problems parsing panel-timing (%d)\n", node, err);
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return err;
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}
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videomode_from_timing(&timing, &video);
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@@ -487,11 +487,6 @@ static int aty128_encode_var(struct fb_var_screeninfo *var,
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const struct aty128fb_par *par);
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static int aty128_decode_var(struct fb_var_screeninfo *var,
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struct aty128fb_par *par);
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#if 0
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static void aty128_get_pllinfo(struct aty128fb_par *par, void __iomem *bios);
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static void __iomem *aty128_map_ROM(struct pci_dev *pdev,
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const struct aty128fb_par *par);
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#endif
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static void aty128_timings(struct aty128fb_par *par);
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static void aty128_init_engine(struct aty128fb_par *par);
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static void aty128_reset_engine(const struct aty128fb_par *par);
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@@ -1665,19 +1660,6 @@ static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
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struct aty128fb_par *par)
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{
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if (par->chip_gen == rage_M3) {
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#if 0
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/* Note: For now, on M3, we set palette on both heads, which may
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* be useless. Can someone with a M3 check this ?
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*
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* This code would still be useful if using the second CRTC to
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* do mirroring
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*/
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aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) |
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DAC_PALETTE_ACCESS_CNTL);
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aty_st_8(PALETTE_INDEX, regno);
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aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
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#endif
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aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
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~DAC_PALETTE_ACCESS_CNTL);
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}
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@@ -1188,19 +1188,6 @@ static int aty_crtc_to_var(const struct crtc *crtc,
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(c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
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switch (pix_width) {
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#if 0
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case CRTC_PIX_WIDTH_4BPP:
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bpp = 4;
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var->red.offset = 0;
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var->red.length = 8;
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var->green.offset = 0;
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var->green.length = 8;
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var->blue.offset = 0;
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var->blue.length = 8;
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var->transp.offset = 0;
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var->transp.length = 0;
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break;
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#endif
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case CRTC_PIX_WIDTH_8BPP:
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bpp = 8;
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var->red.offset = 0;
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@@ -1466,11 +1453,6 @@ static int atyfb_set_par(struct fb_info *info)
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var->bits_per_pixel,
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par->crtc.vxres * var->bits_per_pixel / 8);
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#endif /* CONFIG_BOOTX_TEXT */
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#if 0
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/* switch to accelerator mode */
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if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
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aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
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#endif
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#ifdef DEBUG
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{
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/* dump non shadow CRTC, pll, LCD registers */
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@@ -2395,17 +2377,6 @@ static int aty_init(struct fb_info *info)
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case CLK_IBMRGB514:
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par->pll_ops = &aty_pll_ibm514;
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break;
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#endif
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#if 0 /* dead code */
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case CLK_STG1703:
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par->pll_ops = &aty_pll_stg1703;
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break;
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case CLK_CH8398:
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par->pll_ops = &aty_pll_ch8398;
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break;
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case CLK_ATT20C408:
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par->pll_ops = &aty_pll_att20c408;
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break;
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#endif
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default:
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PRINTKI("aty_init: CLK type not implemented yet!");
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@@ -2217,8 +2217,7 @@ static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
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char *buf, loff_t off, size_t count)
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{
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struct device *dev = container_of(kobj, struct device, kobj);
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struct pci_dev *pdev = to_pci_dev(dev);
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struct fb_info *info = pci_get_drvdata(pdev);
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struct fb_info *info = dev_get_drvdata(dev);
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struct radeonfb_info *rinfo = info->par;
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return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
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@@ -2230,8 +2229,7 @@ static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
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char *buf, loff_t off, size_t count)
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{
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struct device *dev = container_of(kobj, struct device, kobj);
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struct pci_dev *pdev = to_pci_dev(dev);
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struct fb_info *info = pci_get_drvdata(pdev);
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struct fb_info *info = dev_get_drvdata(dev);
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struct radeonfb_info *rinfo = info->par;
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return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
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@@ -1234,7 +1234,7 @@ static int au1200fb_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
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struct au1200fb_device *fbdev = info->par;
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return dma_mmap_attrs(fbdev->dev, vma, fbdev->fb_mem, fbdev->fb_phys,
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fbdev->fb_len, DMA_ATTR_NON_CONSISTENT);
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fbdev->fb_len, 0);
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}
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static void set_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
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@@ -1692,8 +1692,7 @@ static int au1200fb_drv_probe(struct platform_device *dev)
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fbdev->fb_mem = dmam_alloc_attrs(&dev->dev,
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PAGE_ALIGN(fbdev->fb_len),
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&fbdev->fb_phys, GFP_KERNEL,
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DMA_ATTR_NON_CONSISTENT);
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&fbdev->fb_phys, GFP_KERNEL, 0);
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if (!fbdev->fb_mem) {
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print_err("fail to allocate framebuffer (size: %dK))",
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fbdev->fb_len / 1024);
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@@ -1058,7 +1058,7 @@ int
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fb_blank(struct fb_info *info, int blank)
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{
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struct fb_event event;
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int ret = -EINVAL, early_ret;
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int ret = -EINVAL;
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if (blank > FB_BLANK_POWERDOWN)
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blank = FB_BLANK_POWERDOWN;
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@@ -1066,21 +1066,11 @@ fb_blank(struct fb_info *info, int blank)
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event.info = info;
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event.data = ␣
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early_ret = fb_notifier_call_chain(FB_EARLY_EVENT_BLANK, &event);
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if (info->fbops->fb_blank)
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ret = info->fbops->fb_blank(blank, info);
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if (!ret)
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fb_notifier_call_chain(FB_EVENT_BLANK, &event);
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else {
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/*
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* if fb_blank is failed then revert effects of
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* the early blank event.
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*/
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if (!early_ret)
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fb_notifier_call_chain(FB_R_EARLY_EVENT_BLANK, &event);
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}
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return ret;
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}
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@@ -1957,7 +1947,7 @@ int fb_new_modelist(struct fb_info *info)
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struct list_head *pos, *n;
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struct fb_modelist *modelist;
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struct fb_videomode *m, mode;
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int err = 1;
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int err;
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list_for_each_safe(pos, n, &info->modelist) {
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modelist = list_entry(pos, struct fb_modelist, list);
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@@ -999,98 +999,6 @@ void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs)
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DPRINTK("========================================\n");
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}
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/**
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* fb_edid_add_monspecs() - add monitor video modes from E-EDID data
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* @edid: 128 byte array with an E-EDID block
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* @spacs: monitor specs to be extended
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*/
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void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs)
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{
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unsigned char *block;
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struct fb_videomode *m;
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int num = 0, i;
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u8 svd[64], edt[(128 - 4) / DETAILED_TIMING_DESCRIPTION_SIZE];
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u8 pos = 4, svd_n = 0;
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if (!edid)
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return;
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if (!edid_checksum(edid))
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return;
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if (edid[0] != 0x2 ||
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edid[2] < 4 || edid[2] > 128 - DETAILED_TIMING_DESCRIPTION_SIZE)
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return;
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DPRINTK(" Short Video Descriptors\n");
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while (pos < edid[2]) {
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u8 len = edid[pos] & 0x1f, type = (edid[pos] >> 5) & 7;
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pr_debug("Data block %u of %u bytes\n", type, len);
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if (type == 2) {
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for (i = pos; i < pos + len; i++) {
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u8 idx = edid[pos + i] & 0x7f;
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svd[svd_n++] = idx;
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pr_debug("N%sative mode #%d\n",
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edid[pos + i] & 0x80 ? "" : "on-n", idx);
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}
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} else if (type == 3 && len >= 3) {
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/* Check Vendor Specific Data Block. For HDMI,
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it is always 00-0C-03 for HDMI Licensing, LLC. */
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if (edid[pos + 1] == 3 && edid[pos + 2] == 0xc &&
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edid[pos + 3] == 0)
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specs->misc |= FB_MISC_HDMI;
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}
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pos += len + 1;
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}
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block = edid + edid[2];
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DPRINTK(" Extended Detailed Timings\n");
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for (i = 0; i < (128 - edid[2]) / DETAILED_TIMING_DESCRIPTION_SIZE;
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i++, block += DETAILED_TIMING_DESCRIPTION_SIZE)
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if (PIXEL_CLOCK != 0)
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edt[num++] = block - edid;
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/* Yikes, EDID data is totally useless */
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if (!(num + svd_n))
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return;
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m = kcalloc(specs->modedb_len + num + svd_n,
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sizeof(struct fb_videomode),
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GFP_KERNEL);
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if (!m)
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return;
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memcpy(m, specs->modedb, specs->modedb_len * sizeof(struct fb_videomode));
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for (i = specs->modedb_len; i < specs->modedb_len + num; i++) {
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get_detailed_timing(edid + edt[i - specs->modedb_len], &m[i]);
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if (i == specs->modedb_len)
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m[i].flag |= FB_MODE_IS_FIRST;
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pr_debug("Adding %ux%u@%u\n", m[i].xres, m[i].yres, m[i].refresh);
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}
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for (i = specs->modedb_len + num; i < specs->modedb_len + num + svd_n; i++) {
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int idx = svd[i - specs->modedb_len - num];
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if (!idx || idx >= ARRAY_SIZE(cea_modes)) {
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pr_warn("Reserved SVD code %d\n", idx);
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} else if (!cea_modes[idx].xres) {
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pr_warn("Unimplemented SVD code %d\n", idx);
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} else {
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memcpy(&m[i], cea_modes + idx, sizeof(m[i]));
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pr_debug("Adding SVD #%d: %ux%u@%u\n", idx,
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m[i].xres, m[i].yres, m[i].refresh);
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}
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}
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kfree(specs->modedb);
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specs->modedb = m;
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specs->modedb_len = specs->modedb_len + num + svd_n;
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}
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/*
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* VESA Generalized Timing Formula (GTF)
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*/
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@@ -1500,9 +1408,6 @@ int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var)
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void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs)
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{
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}
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void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs)
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{
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}
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void fb_destroy_modedb(struct fb_videomode *modedb)
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{
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}
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@@ -1610,7 +1515,6 @@ EXPORT_SYMBOL(fb_firmware_edid);
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EXPORT_SYMBOL(fb_parse_edid);
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EXPORT_SYMBOL(fb_edid_to_monspecs);
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EXPORT_SYMBOL(fb_edid_add_monspecs);
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EXPORT_SYMBOL(fb_get_mode);
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EXPORT_SYMBOL(fb_validate_mode);
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EXPORT_SYMBOL(fb_destroy_modedb);
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|
@@ -289,63 +289,6 @@ static const struct fb_videomode modedb[] = {
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};
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#ifdef CONFIG_FB_MODE_HELPERS
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const struct fb_videomode cea_modes[65] = {
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/* #1: 640x480p@59.94/60Hz */
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[1] = {
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NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0,
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FB_VMODE_NONINTERLACED, 0,
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},
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/* #3: 720x480p@59.94/60Hz */
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[3] = {
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NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
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FB_VMODE_NONINTERLACED, 0,
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},
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/* #5: 1920x1080i@59.94/60Hz */
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[5] = {
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NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5,
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FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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FB_VMODE_INTERLACED, 0,
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},
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/* #7: 720(1440)x480iH@59.94/60Hz */
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[7] = {
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NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0,
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FB_VMODE_INTERLACED, 0,
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},
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/* #9: 720(1440)x240pH@59.94/60Hz */
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[9] = {
|
||||
NULL, 60, 1440, 240, 18554, 114, 38, 16, 4, 124, 3, 0,
|
||||
FB_VMODE_NONINTERLACED, 0,
|
||||
},
|
||||
/* #18: 720x576pH@50Hz */
|
||||
[18] = {
|
||||
NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
|
||||
FB_VMODE_NONINTERLACED, 0,
|
||||
},
|
||||
/* #19: 1280x720p@50Hz */
|
||||
[19] = {
|
||||
NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
|
||||
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
|
||||
FB_VMODE_NONINTERLACED, 0,
|
||||
},
|
||||
/* #20: 1920x1080i@50Hz */
|
||||
[20] = {
|
||||
NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5,
|
||||
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
|
||||
FB_VMODE_INTERLACED, 0,
|
||||
},
|
||||
/* #32: 1920x1080p@23.98/24Hz */
|
||||
[32] = {
|
||||
NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
|
||||
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
|
||||
FB_VMODE_NONINTERLACED, 0,
|
||||
},
|
||||
/* #35: (2880)x480p4x@59.94/60Hz */
|
||||
[35] = {
|
||||
NULL, 60, 2880, 480, 9250, 240, 64, 30, 9, 248, 6, 0,
|
||||
FB_VMODE_NONINTERLACED, 0,
|
||||
},
|
||||
};
|
||||
|
||||
const struct fb_videomode vesa_modes[] = {
|
||||
/* 0 640x350-85 VESA */
|
||||
{ NULL, 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3,
|
||||
|
@@ -122,28 +122,13 @@ static void efifb_copy_bmp(u8 *src, u32 *dst, int width, struct screen_info *si)
|
||||
*/
|
||||
static bool efifb_bgrt_sanity_check(struct screen_info *si, u32 bmp_width)
|
||||
{
|
||||
static const int default_resolutions[][2] = {
|
||||
{ 800, 600 },
|
||||
{ 1024, 768 },
|
||||
{ 1280, 1024 },
|
||||
};
|
||||
u32 i, right_margin;
|
||||
/*
|
||||
* All x86 firmwares horizontally center the image (the yoffset
|
||||
* calculations differ between boards, but xoffset is predictable).
|
||||
*/
|
||||
u32 expected_xoffset = (si->lfb_width - bmp_width) / 2;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(default_resolutions); i++) {
|
||||
if (default_resolutions[i][0] == si->lfb_width &&
|
||||
default_resolutions[i][1] == si->lfb_height)
|
||||
break;
|
||||
}
|
||||
/* If not a default resolution used for textmode, this should be fine */
|
||||
if (i >= ARRAY_SIZE(default_resolutions))
|
||||
return true;
|
||||
|
||||
/* If the right margin is 5 times smaller then the left one, reject */
|
||||
right_margin = si->lfb_width - (bgrt_tab.image_offset_x + bmp_width);
|
||||
if (right_margin < (bgrt_tab.image_offset_x / 5))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
return bgrt_tab.image_offset_x == expected_xoffset;
|
||||
}
|
||||
#else
|
||||
static bool efifb_bgrt_sanity_check(struct screen_info *si, u32 bmp_width)
|
||||
|
@@ -153,13 +153,11 @@ EXPORT_SYMBOL_GPL(mmp_get_path);
|
||||
struct mmp_path *mmp_register_path(struct mmp_path_info *info)
|
||||
{
|
||||
int i;
|
||||
size_t size;
|
||||
struct mmp_path *path = NULL;
|
||||
struct mmp_panel *panel;
|
||||
|
||||
size = sizeof(struct mmp_path)
|
||||
+ sizeof(struct mmp_overlay) * info->overlay_num;
|
||||
path = kzalloc(size, GFP_KERNEL);
|
||||
path = kzalloc(struct_size(path, overlays, info->overlay_num),
|
||||
GFP_KERNEL);
|
||||
if (!path)
|
||||
return NULL;
|
||||
|
||||
|
@@ -612,7 +612,6 @@ static int mmpfb_probe(struct platform_device *pdev)
|
||||
ret = -ENOMEM;
|
||||
goto failed_destroy_mutex;
|
||||
}
|
||||
memset(fbi->fb_start, 0, fbi->fb_size);
|
||||
dev_info(fbi->dev, "fb %dk allocated\n", fbi->fb_size/1024);
|
||||
|
||||
/* fb power on */
|
||||
|
@@ -123,8 +123,6 @@ void nvidia_bl_init(struct nvidia_par *par)
|
||||
|
||||
printk("nvidia: Backlight initialized (%s)\n", name);
|
||||
|
||||
return;
|
||||
|
||||
error:
|
||||
return;
|
||||
}
|
||||
|
@@ -119,34 +119,10 @@ u8 NVReadMiscOut(struct nvidia_par *par)
|
||||
{
|
||||
return (VGA_RD08(par->PVIO, VGA_MIS_R));
|
||||
}
|
||||
#if 0
|
||||
void NVEnablePalette(struct nvidia_par *par)
|
||||
{
|
||||
volatile u8 tmp;
|
||||
|
||||
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
|
||||
VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
|
||||
par->paletteEnabled = 1;
|
||||
}
|
||||
void NVDisablePalette(struct nvidia_par *par)
|
||||
{
|
||||
volatile u8 tmp;
|
||||
|
||||
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
|
||||
VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
|
||||
par->paletteEnabled = 0;
|
||||
}
|
||||
#endif /* 0 */
|
||||
void NVWriteDacMask(struct nvidia_par *par, u8 value)
|
||||
{
|
||||
VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
|
||||
}
|
||||
#if 0
|
||||
u8 NVReadDacMask(struct nvidia_par *par)
|
||||
{
|
||||
return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
|
||||
}
|
||||
#endif /* 0 */
|
||||
void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
|
||||
{
|
||||
VGA_WR08(par->PDIO, VGA_PEL_IR, value);
|
||||
|
@@ -49,6 +49,7 @@ config FB_OMAP2_PANEL_DSI_CM
|
||||
config FB_OMAP2_PANEL_SONY_ACX565AKM
|
||||
tristate "ACX565AKM Panel"
|
||||
depends on SPI && BACKLIGHT_CLASS_DEVICE
|
||||
depends on DRM_PANEL_SONY_ACX565AKM = n
|
||||
help
|
||||
This is the LCD panel used on Nokia N900
|
||||
|
||||
@@ -61,18 +62,21 @@ config FB_OMAP2_PANEL_LGPHILIPS_LB035Q02
|
||||
config FB_OMAP2_PANEL_SHARP_LS037V7DW01
|
||||
tristate "Sharp LS037V7DW01 LCD Panel"
|
||||
depends on BACKLIGHT_CLASS_DEVICE
|
||||
depends on DRM_PANEL_SHARP_LS037V7DW01 = n
|
||||
help
|
||||
LCD Panel used in TI's SDP3430 and EVM boards
|
||||
|
||||
config FB_OMAP2_PANEL_TPO_TD028TTEC1
|
||||
tristate "TPO TD028TTEC1 LCD Panel"
|
||||
depends on SPI
|
||||
depends on DRM_PANEL_TPO_TD028TTEC1 = n
|
||||
help
|
||||
LCD panel used in Openmoko.
|
||||
|
||||
config FB_OMAP2_PANEL_TPO_TD043MTEA1
|
||||
tristate "TPO TD043MTEA1 LCD Panel"
|
||||
depends on SPI
|
||||
depends on DRM_PANEL_TPO_TD043MTEA1 = n
|
||||
help
|
||||
LCD Panel used in OMAP3 Pandora
|
||||
|
||||
@@ -80,6 +84,7 @@ config FB_OMAP2_PANEL_NEC_NL8048HL11
|
||||
tristate "NEC NL8048HL11 Panel"
|
||||
depends on SPI
|
||||
depends on BACKLIGHT_CLASS_DEVICE
|
||||
depends on DRM_PANEL_NEC_NL8048HL11 = n
|
||||
help
|
||||
This NEC NL8048HL11 panel is TFT LCD used in the
|
||||
Zoom2/3/3630 sdp boards.
|
||||
|
@@ -458,13 +458,11 @@ static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
|
||||
set_color_bitfields(var);
|
||||
|
||||
if (var->vmode & FB_VMODE_YWRAP) {
|
||||
if (var->xoffset || var->yoffset < 0 ||
|
||||
var->yoffset >= var->yres_virtual) {
|
||||
if (var->xoffset || var->yoffset >= var->yres_virtual) {
|
||||
var->xoffset = var->yoffset = 0;
|
||||
} else {
|
||||
if (var->xoffset > var->xres_virtual - var->xres ||
|
||||
var->yoffset > var->yres_virtual - var->yres ||
|
||||
var->xoffset < 0 || var->yoffset < 0)
|
||||
var->yoffset > var->yres_virtual - var->yres)
|
||||
var->xoffset = var->yoffset = 0;
|
||||
}
|
||||
} else {
|
||||
|
@@ -1594,6 +1594,7 @@ sh_mobile_lcdc_overlay_fb_init(struct sh_mobile_lcdc_overlay *ovl)
|
||||
case V4L2_PIX_FMT_NV12:
|
||||
case V4L2_PIX_FMT_NV21:
|
||||
info->fix.ypanstep = 2;
|
||||
/* Fall through */
|
||||
case V4L2_PIX_FMT_NV16:
|
||||
case V4L2_PIX_FMT_NV61:
|
||||
info->fix.xpanstep = 2;
|
||||
@@ -2084,6 +2085,7 @@ sh_mobile_lcdc_channel_fb_init(struct sh_mobile_lcdc_chan *ch,
|
||||
case V4L2_PIX_FMT_NV12:
|
||||
case V4L2_PIX_FMT_NV21:
|
||||
info->fix.ypanstep = 2;
|
||||
/* Fall through */
|
||||
case V4L2_PIX_FMT_NV16:
|
||||
case V4L2_PIX_FMT_NV61:
|
||||
info->fix.xpanstep = 2;
|
||||
|
@@ -1694,10 +1694,8 @@ static void smtcfb_pci_remove(struct pci_dev *pdev)
|
||||
|
||||
static int __maybe_unused smtcfb_pci_suspend(struct device *device)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(device);
|
||||
struct smtcfb_info *sfb;
|
||||
struct smtcfb_info *sfb = dev_get_drvdata(device);
|
||||
|
||||
sfb = pci_get_drvdata(pdev);
|
||||
|
||||
/* set the hw in sleep mode use external clock and self memory refresh
|
||||
* so that we can turn off internal PLLs later on
|
||||
@@ -1717,10 +1715,8 @@ static int __maybe_unused smtcfb_pci_suspend(struct device *device)
|
||||
|
||||
static int __maybe_unused smtcfb_pci_resume(struct device *device)
|
||||
{
|
||||
struct pci_dev *pdev = to_pci_dev(device);
|
||||
struct smtcfb_info *sfb;
|
||||
struct smtcfb_info *sfb = dev_get_drvdata(device);
|
||||
|
||||
sfb = pci_get_drvdata(pdev);
|
||||
|
||||
/* reinit hardware */
|
||||
sm7xx_init_hw();
|
||||
|
@@ -28,6 +28,7 @@
|
||||
#define SSD1307FB_SET_COL_RANGE 0x21
|
||||
#define SSD1307FB_SET_PAGE_RANGE 0x22
|
||||
#define SSD1307FB_CONTRAST 0x81
|
||||
#define SSD1307FB_SET_LOOKUP_TABLE 0x91
|
||||
#define SSD1307FB_CHARGE_PUMP 0x8d
|
||||
#define SSD1307FB_SEG_REMAP_ON 0xa1
|
||||
#define SSD1307FB_DISPLAY_OFF 0xae
|
||||
@@ -36,6 +37,7 @@
|
||||
#define SSD1307FB_START_PAGE_ADDRESS 0xb0
|
||||
#define SSD1307FB_SET_DISPLAY_OFFSET 0xd3
|
||||
#define SSD1307FB_SET_CLOCK_FREQ 0xd5
|
||||
#define SSD1307FB_SET_AREA_COLOR_MODE 0xd8
|
||||
#define SSD1307FB_SET_PRECHARGE_PERIOD 0xd9
|
||||
#define SSD1307FB_SET_COM_PINS_CONFIG 0xda
|
||||
#define SSD1307FB_SET_VCOMH 0xdb
|
||||
@@ -58,10 +60,14 @@ struct ssd1307fb_deviceinfo {
|
||||
};
|
||||
|
||||
struct ssd1307fb_par {
|
||||
u32 com_invdir;
|
||||
u32 com_lrremap;
|
||||
unsigned area_color_enable : 1;
|
||||
unsigned com_invdir : 1;
|
||||
unsigned com_lrremap : 1;
|
||||
unsigned com_seq : 1;
|
||||
unsigned lookup_table_set : 1;
|
||||
unsigned low_power : 1;
|
||||
unsigned seg_remap : 1;
|
||||
u32 com_offset;
|
||||
u32 com_seq;
|
||||
u32 contrast;
|
||||
u32 dclk_div;
|
||||
u32 dclk_frq;
|
||||
@@ -69,6 +75,7 @@ struct ssd1307fb_par {
|
||||
struct i2c_client *client;
|
||||
u32 height;
|
||||
struct fb_info *info;
|
||||
u8 lookup_table[4];
|
||||
u32 page_offset;
|
||||
u32 prechargep1;
|
||||
u32 prechargep2;
|
||||
@@ -76,7 +83,6 @@ struct ssd1307fb_par {
|
||||
u32 pwm_period;
|
||||
struct gpio_desc *reset;
|
||||
struct regulator *vbat_reg;
|
||||
u32 seg_remap;
|
||||
u32 vcomh;
|
||||
u32 width;
|
||||
};
|
||||
@@ -98,6 +104,9 @@ static const struct fb_fix_screeninfo ssd1307fb_fix = {
|
||||
|
||||
static const struct fb_var_screeninfo ssd1307fb_var = {
|
||||
.bits_per_pixel = 1,
|
||||
.red = { .length = 1 },
|
||||
.green = { .length = 1 },
|
||||
.blue = { .length = 1 },
|
||||
};
|
||||
|
||||
static struct ssd1307fb_array *ssd1307fb_alloc_array(u32 len, u8 type)
|
||||
@@ -149,11 +158,12 @@ static inline int ssd1307fb_write_cmd(struct i2c_client *client, u8 cmd)
|
||||
static void ssd1307fb_update_display(struct ssd1307fb_par *par)
|
||||
{
|
||||
struct ssd1307fb_array *array;
|
||||
u8 *vmem = par->info->screen_base;
|
||||
u8 *vmem = par->info->screen_buffer;
|
||||
unsigned int line_length = par->info->fix.line_length;
|
||||
unsigned int pages = DIV_ROUND_UP(par->height, 8);
|
||||
int i, j, k;
|
||||
|
||||
array = ssd1307fb_alloc_array(par->width * par->height / 8,
|
||||
SSD1307FB_DATA);
|
||||
array = ssd1307fb_alloc_array(par->width * pages, SSD1307FB_DATA);
|
||||
if (!array)
|
||||
return;
|
||||
|
||||
@@ -186,22 +196,24 @@ static void ssd1307fb_update_display(struct ssd1307fb_par *par)
|
||||
* (5) A4 B4 C4 D4 E4 F4 G4 H4
|
||||
*/
|
||||
|
||||
for (i = 0; i < (par->height / 8); i++) {
|
||||
for (i = 0; i < pages; i++) {
|
||||
for (j = 0; j < par->width; j++) {
|
||||
int m = 8;
|
||||
u32 array_idx = i * par->width + j;
|
||||
array->data[array_idx] = 0;
|
||||
for (k = 0; k < 8; k++) {
|
||||
u32 page_length = par->width * i;
|
||||
u32 index = page_length + (par->width * k + j) / 8;
|
||||
u8 byte = *(vmem + index);
|
||||
u8 bit = byte & (1 << (j % 8));
|
||||
bit = bit >> (j % 8);
|
||||
/* Last page may be partial */
|
||||
if (i + 1 == pages && par->height % 8)
|
||||
m = par->height % 8;
|
||||
for (k = 0; k < m; k++) {
|
||||
u8 byte = vmem[(8 * i + k) * line_length +
|
||||
j / 8];
|
||||
u8 bit = (byte >> (j % 8)) & 1;
|
||||
array->data[array_idx] |= bit << k;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ssd1307fb_write_array(par->client, array, par->width * par->height / 8);
|
||||
ssd1307fb_write_array(par->client, array, par->width * pages);
|
||||
kfree(array);
|
||||
}
|
||||
|
||||
@@ -212,7 +224,7 @@ static ssize_t ssd1307fb_write(struct fb_info *info, const char __user *buf,
|
||||
struct ssd1307fb_par *par = info->par;
|
||||
unsigned long total_size;
|
||||
unsigned long p = *ppos;
|
||||
u8 __iomem *dst;
|
||||
void *dst;
|
||||
|
||||
total_size = info->fix.smem_len;
|
||||
|
||||
@@ -225,7 +237,7 @@ static ssize_t ssd1307fb_write(struct fb_info *info, const char __user *buf,
|
||||
if (!count)
|
||||
return -EINVAL;
|
||||
|
||||
dst = (void __force *) (info->screen_base + p);
|
||||
dst = info->screen_buffer + p;
|
||||
|
||||
if (copy_from_user(dst, buf, count))
|
||||
return -EFAULT;
|
||||
@@ -312,7 +324,7 @@ static int ssd1307fb_init(struct ssd1307fb_par *par)
|
||||
|
||||
dev_dbg(&par->client->dev, "Using PWM%d with a %dns period.\n",
|
||||
par->pwm->pwm, par->pwm_period);
|
||||
};
|
||||
}
|
||||
|
||||
/* Set initial contrast */
|
||||
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CONTRAST);
|
||||
@@ -328,10 +340,10 @@ static int ssd1307fb_init(struct ssd1307fb_par *par)
|
||||
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
};
|
||||
}
|
||||
|
||||
/* Set COM direction */
|
||||
com_invdir = 0xc0 | (par->com_invdir & 0x1) << 3;
|
||||
com_invdir = 0xc0 | par->com_invdir << 3;
|
||||
ret = ssd1307fb_write_cmd(par->client, com_invdir);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
@@ -364,6 +376,22 @@ static int ssd1307fb_init(struct ssd1307fb_par *par)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Set Set Area Color Mode ON/OFF & Low Power Display Mode */
|
||||
if (par->area_color_enable || par->low_power) {
|
||||
u32 mode;
|
||||
|
||||
ret = ssd1307fb_write_cmd(par->client,
|
||||
SSD1307FB_SET_AREA_COLOR_MODE);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
mode = (par->area_color_enable ? 0x30 : 0) |
|
||||
(par->low_power ? 5 : 0);
|
||||
ret = ssd1307fb_write_cmd(par->client, mode);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Set precharge period in number of ticks from the internal clock */
|
||||
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_PRECHARGE_PERIOD);
|
||||
if (ret < 0)
|
||||
@@ -379,8 +407,7 @@ static int ssd1307fb_init(struct ssd1307fb_par *par)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
compins = 0x02 | !(par->com_seq & 0x1) << 4
|
||||
| (par->com_lrremap & 0x1) << 5;
|
||||
compins = 0x02 | !par->com_seq << 4 | par->com_lrremap << 5;
|
||||
ret = ssd1307fb_write_cmd(par->client, compins);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
@@ -404,6 +431,28 @@ static int ssd1307fb_init(struct ssd1307fb_par *par)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Set lookup table */
|
||||
if (par->lookup_table_set) {
|
||||
int i;
|
||||
|
||||
ret = ssd1307fb_write_cmd(par->client,
|
||||
SSD1307FB_SET_LOOKUP_TABLE);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(par->lookup_table); ++i) {
|
||||
u8 val = par->lookup_table[i];
|
||||
|
||||
if (val < 31 || val > 63)
|
||||
dev_warn(&par->client->dev,
|
||||
"lookup table index %d value out of range 31 <= %d <= 63\n",
|
||||
i, val);
|
||||
ret = ssd1307fb_write_cmd(par->client, val);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch to horizontal addressing mode */
|
||||
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_ADDRESS_MODE);
|
||||
if (ret < 0)
|
||||
@@ -432,12 +481,13 @@ static int ssd1307fb_init(struct ssd1307fb_par *par)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = ssd1307fb_write_cmd(par->client, 0x0);
|
||||
ret = ssd1307fb_write_cmd(par->client, par->page_offset);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = ssd1307fb_write_cmd(par->client,
|
||||
par->page_offset + (par->height / 8) - 1);
|
||||
par->page_offset +
|
||||
DIV_ROUND_UP(par->height, 8) - 1);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
@@ -546,7 +596,7 @@ static int ssd1307fb_probe(struct i2c_client *client,
|
||||
struct fb_deferred_io *ssd1307fb_defio;
|
||||
u32 vmem_size;
|
||||
struct ssd1307fb_par *par;
|
||||
u8 *vmem;
|
||||
void *vmem;
|
||||
int ret;
|
||||
|
||||
if (!node) {
|
||||
@@ -603,19 +653,29 @@ static int ssd1307fb_probe(struct i2c_client *client,
|
||||
if (of_property_read_u32(node, "solomon,prechargep2", &par->prechargep2))
|
||||
par->prechargep2 = 2;
|
||||
|
||||
if (!of_property_read_u8_array(node, "solomon,lookup-table",
|
||||
par->lookup_table,
|
||||
ARRAY_SIZE(par->lookup_table)))
|
||||
par->lookup_table_set = 1;
|
||||
|
||||
par->seg_remap = !of_property_read_bool(node, "solomon,segment-no-remap");
|
||||
par->com_seq = of_property_read_bool(node, "solomon,com-seq");
|
||||
par->com_lrremap = of_property_read_bool(node, "solomon,com-lrremap");
|
||||
par->com_invdir = of_property_read_bool(node, "solomon,com-invdir");
|
||||
par->area_color_enable =
|
||||
of_property_read_bool(node, "solomon,area-color-enable");
|
||||
par->low_power = of_property_read_bool(node, "solomon,low-power");
|
||||
|
||||
par->contrast = 127;
|
||||
par->vcomh = par->device_info->default_vcomh;
|
||||
|
||||
/* Setup display timing */
|
||||
par->dclk_div = par->device_info->default_dclk_div;
|
||||
par->dclk_frq = par->device_info->default_dclk_frq;
|
||||
if (of_property_read_u32(node, "solomon,dclk-div", &par->dclk_div))
|
||||
par->dclk_div = par->device_info->default_dclk_div;
|
||||
if (of_property_read_u32(node, "solomon,dclk-frq", &par->dclk_frq))
|
||||
par->dclk_frq = par->device_info->default_dclk_frq;
|
||||
|
||||
vmem_size = par->width * par->height / 8;
|
||||
vmem_size = DIV_ROUND_UP(par->width, 8) * par->height;
|
||||
|
||||
vmem = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
||||
get_order(vmem_size));
|
||||
@@ -638,7 +698,7 @@ static int ssd1307fb_probe(struct i2c_client *client,
|
||||
|
||||
info->fbops = &ssd1307fb_ops;
|
||||
info->fix = ssd1307fb_fix;
|
||||
info->fix.line_length = par->width / 8;
|
||||
info->fix.line_length = DIV_ROUND_UP(par->width, 8);
|
||||
info->fbdefio = ssd1307fb_defio;
|
||||
|
||||
info->var = ssd1307fb_var;
|
||||
@@ -647,14 +707,7 @@ static int ssd1307fb_probe(struct i2c_client *client,
|
||||
info->var.yres = par->height;
|
||||
info->var.yres_virtual = par->height;
|
||||
|
||||
info->var.red.length = 1;
|
||||
info->var.red.offset = 0;
|
||||
info->var.green.length = 1;
|
||||
info->var.green.offset = 0;
|
||||
info->var.blue.length = 1;
|
||||
info->var.blue.offset = 0;
|
||||
|
||||
info->screen_base = (u8 __force __iomem *)vmem;
|
||||
info->screen_buffer = vmem;
|
||||
info->fix.smem_start = __pa(vmem);
|
||||
info->fix.smem_len = vmem_size;
|
||||
|
||||
@@ -713,7 +766,7 @@ panel_init_error:
|
||||
if (par->device_info->need_pwm) {
|
||||
pwm_disable(par->pwm);
|
||||
pwm_put(par->pwm);
|
||||
};
|
||||
}
|
||||
regulator_enable_error:
|
||||
if (par->vbat_reg)
|
||||
regulator_disable(par->vbat_reg);
|
||||
@@ -737,7 +790,7 @@ static int ssd1307fb_remove(struct i2c_client *client)
|
||||
if (par->device_info->need_pwm) {
|
||||
pwm_disable(par->pwm);
|
||||
pwm_put(par->pwm);
|
||||
};
|
||||
}
|
||||
fb_deferred_io_cleanup(info);
|
||||
__free_pages(__va(info->fix.smem_start), get_order(info->fix.smem_len));
|
||||
framebuffer_release(info);
|
||||
|
@@ -1183,7 +1183,7 @@ static int dlfb_ops_blank(int blank_mode, struct fb_info *info)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct fb_ops dlfb_ops = {
|
||||
static const struct fb_ops dlfb_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.fb_read = fb_sys_read,
|
||||
.fb_write = dlfb_ops_write,
|
||||
|
@@ -221,49 +221,6 @@ void viafb_release_dma(void)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(viafb_release_dma);
|
||||
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* Copy a single buffer from FB memory, synchronously. This code works
|
||||
* but is not currently used.
|
||||
*/
|
||||
void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len)
|
||||
{
|
||||
unsigned long flags;
|
||||
int csr;
|
||||
|
||||
mutex_lock(&viafb_dma_lock);
|
||||
init_completion(&viafb_dma_completion);
|
||||
/*
|
||||
* Program the controller.
|
||||
*/
|
||||
spin_lock_irqsave(&global_dev.reg_lock, flags);
|
||||
viafb_mmio_write(VDMA_CSR0, VDMA_C_ENABLE|VDMA_C_DONE);
|
||||
/* Enable ints; must happen after CSR0 write! */
|
||||
viafb_mmio_write(VDMA_MR0, VDMA_MR_TDIE);
|
||||
viafb_mmio_write(VDMA_MARL0, (int) (paddr & 0xfffffff0));
|
||||
viafb_mmio_write(VDMA_MARH0, (int) ((paddr >> 28) & 0xfff));
|
||||
/* Data sheet suggests DAR0 should be <<4, but it lies */
|
||||
viafb_mmio_write(VDMA_DAR0, offset);
|
||||
viafb_mmio_write(VDMA_DQWCR0, len >> 4);
|
||||
viafb_mmio_write(VDMA_TMR0, 0);
|
||||
viafb_mmio_write(VDMA_DPRL0, 0);
|
||||
viafb_mmio_write(VDMA_DPRH0, 0);
|
||||
viafb_mmio_write(VDMA_PMR0, 0);
|
||||
csr = viafb_mmio_read(VDMA_CSR0);
|
||||
viafb_mmio_write(VDMA_CSR0, VDMA_C_ENABLE|VDMA_C_START);
|
||||
spin_unlock_irqrestore(&global_dev.reg_lock, flags);
|
||||
/*
|
||||
* Now we just wait until the interrupt handler says
|
||||
* we're done.
|
||||
*/
|
||||
wait_for_completion_interruptible(&viafb_dma_completion);
|
||||
viafb_mmio_write(VDMA_MR0, 0); /* Reset int enable */
|
||||
mutex_unlock(&viafb_dma_lock);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(viafb_dma_copy_out);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Do a scatter/gather DMA copy from FB memory. You must have done
|
||||
* a successful call to viafb_request_dma() first.
|
||||
|
@@ -119,17 +119,20 @@ int of_get_display_timing(const struct device_node *np, const char *name,
|
||||
struct display_timing *dt)
|
||||
{
|
||||
struct device_node *timing_np;
|
||||
int ret;
|
||||
|
||||
if (!np)
|
||||
return -EINVAL;
|
||||
|
||||
timing_np = of_get_child_by_name(np, name);
|
||||
if (!timing_np) {
|
||||
pr_err("%pOF: could not find node '%s'\n", np, name);
|
||||
if (!timing_np)
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
return of_parse_display_timing(timing_np, dt);
|
||||
ret = of_parse_display_timing(timing_np, dt);
|
||||
|
||||
of_node_put(timing_np);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_get_display_timing);
|
||||
|
||||
|
Reference in New Issue
Block a user