xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: Add Tauros2 L2 cache controller support

Browse Source 
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
This commit is contained in:
Lennert Buytenhek
2009-11-24 19:33:52 +02:00
committed by Nicolas Pitre
parent edabd38e1a
commit 573a652fb0
6 changed files with 291 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-dove/common.c
View File

@@ -24,6 +24,7 @@
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/timex.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/pci.h>
@@ -760,6 +761,9 @@ void __init dove_init(void)
printk(KERN_INFO "Dove 88AP510 SoC, ");
printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init();
#endif
dove_setup_cpu_mbus();
dove_ge00_shared_data.t_clk = tclk;