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Merge tag 'devicetree-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Browse Source 
Pull devicetree updates from Rob Herring:

 - Convert various DT (non-binding) doc files to ReST

 - Various improvements to device link code

 - Fix __of_attach_node_sysfs refcounting bug

 - Add support for 'memory-region-names' with reserved-memory binding

 - Vendor prefixes for Protonic Holland, BeagleBoard.org, Alps, Check
   Point, Würth Elektronik, U-Boot, Vaisala, Baikal Electronics,
   Shanghai Awinic Technology Co., MikroTik, Silex Insight

 - A bunch more binding conversions to DT schema. Only 3K to go.

 - Add a minimum version check for schema tools

 - Treewide dropping of 'allOf' usage with schema references. Not needed
   in new json-schema spec.

 - Some formatting clean-ups of schemas

* tag 'devicetree-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (194 commits)
  dt-bindings: clock: Add documentation for X1830 bindings.
  dt-bindings: mailbox: Convert imx mu to json-schema
  dt-bindings: power: Convert imx gpcv2 to json-schema
  dt-bindings: power: Convert imx gpc to json-schema
  dt-bindings: Merge gpio-usb-b-connector with usb-connector
  dt-bindings: timer: renesas: cmt: Convert to json-schema
  dt-bindings: clock: Convert i.MX8QXP LPCG to json-schema
  dt-bindings: timer: Convert i.MX GPT to json-schema
  dt-bindings: thermal: rcar-thermal: Add device tree support for r8a7742
  dt-bindings: serial: Add binding for UART pin swap
  dt-bindings: geni-se: Add interconnect binding for GENI QUP
  dt-bindings: geni-se: Convert QUP geni-se bindings to YAML
  dt-bindings: vendor-prefixes: Add Silex Insight vendor prefix
  dt-bindings: input: touchscreen: edt-ft5x06: change reg property
  dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver
  dt-bindings: timer: renesas: mtu2: Convert to json-schema
  of/fdt: Remove redundant kbasename function call
  dt-bindings: clock: Convert i.MX1 clock to json-schema
  dt-bindings: clock: Convert i.MX21 clock to json-schema
  dt-bindings: clock: Convert i.MX25 clock to json-schema
  ...
This commit is contained in:
Linus Torvalds
2020-06-04 20:11:25 -07:00
parent 9d71d3cd9e 8211d1e83a
commit 571d54ed91
469 changed files with 11724 additions and 7420 deletions
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16
Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.txt
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@@ -1,16 +0,0 @@
Calxeda DDR memory controller
Properties:
- compatible : Should be:
- "calxeda,hb-ddr-ctrl" for ECX-1000
- "calxeda,ecx-2000-ddr-ctrl" for ECX-2000
- reg : Address and size for DDR controller registers.
- interrupts : Interrupt for DDR controller.
Example:
memory-controller@fff00000 {
compatible = "calxeda,hb-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};

42
Documentation/devicetree/bindings/memory-controllers/calxeda-ddr-ctrlr.yaml Normal file
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@@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Calxeda DDR memory controller binding
description: |
The Calxeda DDR memory controller is initialised and programmed by the
firmware, but an OS might want to read its registers for error reporting
purposes and to learn about the DRAM topology.
maintainers:
- Andre Przywara <andre.przywara@arm.com>
properties:
compatible:
enum:
- calxeda,hb-ddr-ctrl
- calxeda,ecx-2000-ddr-ctrl
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
memory-controller@fff00000 {
compatible = "calxeda,hb-ddr-ctrl";
reg = <0xfff00000 0x1000>;
interrupts = <0 91 4>;
};

13
Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml
View File

@@ -51,9 +51,7 @@ patternProperties:
maxItems: 1
reg-io-width:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2]
enum: [1, 2]
description:
Data width in bytes (1 or 2). If omitted, default of 1 is used.
@@ -64,11 +62,10 @@ patternProperties:
type: boolean
samsung,srom-timing:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- items:
minItems: 6
maxItems: 6
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
minItems: 6
maxItems: 6
description: |
Array of 6 integers, specifying bank timings in the following order:
Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.

6
Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
View File

@@ -25,9 +25,9 @@ properties:
compatible:
items:
- enum:
- fsl,imx8mn-ddrc
- fsl,imx8mm-ddrc
- fsl,imx8mq-ddrc
- fsl,imx8mn-ddrc
- fsl,imx8mm-ddrc
- fsl,imx8mq-ddrc
- const: fsl,imx8m-ddrc
reg:

76
Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt
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@@ -1,76 +0,0 @@
* Ingenic JZ4780 NAND/external memory controller (NEMC)
This file documents the device tree bindings for the NEMC external memory
controller in Ingenic JZ4780
Required properties:
- compatible: Should be set to one of:
"ingenic,jz4740-nemc" (JZ4740)
"ingenic,jz4780-nemc" (JZ4780)
- reg: Should specify the NEMC controller registers location and length.
- clocks: Clock for the NEMC controller.
- #address-cells: Must be set to 2.
- #size-cells: Must be set to 1.
- ranges: A set of ranges for each bank describing the physical memory layout.
Each should specify the following 4 integer values:
<cs number> 0 <physical address of mapping> <size of mapping>
Each child of the NEMC node describes a device connected to the NEMC.
Required child node properties:
- reg: Should contain at least one register specifier, given in the following
format:
<cs number> <offset> <size>
Multiple registers can be specified across multiple banks. This is needed,
for example, for packaged NAND devices with multiple dies. Such devices
should be grouped into a single node.
Optional child node properties:
- ingenic,nemc-bus-width: Specifies the bus width in bits. Defaults to 8 bits.
- ingenic,nemc-tAS: Address setup time in nanoseconds.
- ingenic,nemc-tAH: Address hold time in nanoseconds.
- ingenic,nemc-tBP: Burst pitch time in nanoseconds.
- ingenic,nemc-tAW: Access wait time in nanoseconds.
- ingenic,nemc-tSTRV: Static memory recovery time in nanoseconds.
If a child node references multiple banks in its "reg" property, the same value
for all optional parameters will be configured for all banks. If any optional
parameters are omitted, they will be left unchanged from whatever they are
configured to when the NEMC device is probed (which may be the reset value as
given in the hardware reference manual, or a value configured by the boot
loader).
Example (NEMC node with a NAND child device attached at CS1):
nemc: nemc@13410000 {
compatible = "ingenic,jz4780-nemc";
reg = <0x13410000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x1b000000 0x1000000
2 0 0x1a000000 0x1000000
3 0 0x19000000 0x1000000
4 0 0x18000000 0x1000000
5 0 0x17000000 0x1000000
6 0 0x16000000 0x1000000>;
clocks = <&cgu JZ4780_CLK_NEMC>;
nand: nand@1 {
compatible = "ingenic,jz4780-nand";
reg = <1 0 0x1000000>;
ingenic,nemc-tAS = <10>;
ingenic,nemc-tAH = <5>;
ingenic,nemc-tBP = <10>;
ingenic,nemc-tAW = <15>;
ingenic,nemc-tSTRV = <100>;
...
};
};

126
Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml Normal file
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@@ -0,0 +1,126 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ingenic SoCs NAND / External Memory Controller (NEMC) devicetree bindings
maintainers:
- Paul Cercueil <paul@crapouillou.net>
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- ingenic,jz4740-nemc
- ingenic,jz4780-nemc
- items:
- const: ingenic,jz4725b-nemc
- const: ingenic,jz4740-nemc
"#address-cells":
const: 2
"#size-cells":
const: 1
ranges: true
reg:
maxItems: 1
clocks:
maxItems: 1
patternProperties:
".*@[0-9]+$":
type: object
properties:
reg:
minItems: 1
maxItems: 255
ingenic,nemc-bus-width:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [8, 16]
description: Specifies the bus width in bits.
ingenic,nemc-tAS:
$ref: /schemas/types.yaml#/definitions/uint32
description: Address setup time in nanoseconds.
ingenic,nemc-tAH:
$ref: /schemas/types.yaml#/definitions/uint32
description: Address hold time in nanoseconds.
ingenic,nemc-tBP:
$ref: /schemas/types.yaml#/definitions/uint32
description: Burst pitch time in nanoseconds.
ingenic,nemc-tAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: Address wait time in nanoseconds.
ingenic,nemc-tSTRV:
$ref: /schemas/types.yaml#/definitions/uint32
description: Static memory recovery time in nanoseconds.
required:
- reg
required:
- compatible
- "#address-cells"
- "#size-cells"
- ranges
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/jz4780-cgu.h>
#include <dt-bindings/gpio/gpio.h>
nemc: memory-controller@13410000 {
compatible = "ingenic,jz4780-nemc";
reg = <0x13410000 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x1b000000 0x1000000>,
<2 0 0x1a000000 0x1000000>,
<3 0 0x19000000 0x1000000>,
<4 0 0x18000000 0x1000000>,
<5 0 0x17000000 0x1000000>,
<6 0 0x16000000 0x1000000>;
clocks = <&cgu JZ4780_CLK_NEMC>;
ethernet@6 {
compatible = "davicom,dm9000";
davicom,no-eeprom;
pinctrl-names = "default";
pinctrl-0 = <&pins_nemc_cs6>;
reg = <6 0 1>, /* addr */
<6 2 1>; /* data */
ingenic,nemc-tAS = <15>;
ingenic,nemc-tAH = <10>;
ingenic,nemc-tBP = <20>;
ingenic,nemc-tAW = <50>;
ingenic,nemc-tSTRV = <100>;
reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
vcc-supply = <&eth0_power>;
interrupt-parent = <&gpe>;
interrupts = <19 4>;
};
};

13
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
View File

@@ -73,10 +73,9 @@ patternProperties:
timings
nvidia,emc-auto-cal-interval:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
description:
pad calibration interval in microseconds
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 2097151
@@ -136,11 +135,10 @@ patternProperties:
value of the EMC_XM2DQSPADCTRL2 register for this set of timings
nvidia,emc-zcal-cnt-long:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
description:
number of EMC clocks to wait before issuing any commands after
clock change
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1023
@@ -150,12 +148,11 @@ patternProperties:
value of the EMC_ZCAL_INTERVAL register for this set of timings
nvidia,emc-configuration:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
description:
EMC timing characterization data. These are the registers (see
section "15.6.2 EMC Registers" in the TRM) whose values need to
be specified, according to the board documentation.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: EMC_RC
- description: EMC_RFC
@@ -340,7 +337,7 @@ examples:
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
reg = <0x70019000 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = "mc";
@@ -352,7 +349,7 @@ examples:
external-memory-controller@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
reg = <0x7001b000 0x1000>;
clocks = <&car TEGRA124_CLK_EMC>;
clock-names = "emc";

5
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
View File

@@ -60,8 +60,7 @@ patternProperties:
maximum: 1066000000
nvidia,emem-configuration:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"15.6.1 MC Registers" in the TRM.
@@ -112,7 +111,7 @@ examples:
- |
memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
reg = <0x70019000 0x1000>;
clocks = <&tegra_car 32>;
clock-names = "mc";

9
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
View File

@@ -56,10 +56,9 @@ patternProperties:
maximum: 900000000
nvidia,emc-auto-cal-interval:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
description:
Pad calibration interval in microseconds.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 2097151
@@ -79,11 +78,10 @@ patternProperties:
Mode Register 0.
nvidia,emc-zcal-cnt-long:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
description:
Number of EMC clocks to wait before issuing any commands after
sending ZCAL_MRW_CMD.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 1023
@@ -98,12 +96,11 @@ patternProperties:
FBIO "read" FIFO periodic resetting enabled.
nvidia,emc-configuration:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
description:
EMC timing characterization data. These are the registers
(see section "18.13.2 EMC Registers" in the TRM) whose values
need to be specified, according to the board documentation.
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: EMC_RC
- description: EMC_RFC

3
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml
View File

@@ -77,8 +77,7 @@ patternProperties:
maximum: 900000000
nvidia,emem-configuration:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"18.13.1 MC Registers" in the TRM.

44
Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.txt
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@@ -1,44 +0,0 @@
DT bindings for Renesas R-Mobile and SH-Mobile memory controllers
=================================================================
Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers.
These memory controllers differ from one SoC variant to another, and are called
by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
(DBSC3)", "SDRAM Bus State Controller (SBSC)").
Currently memory controller device nodes are used only to reference PM
domains, and prevent these PM domains from being powered down, which would
crash the system.
As there exist no actual drivers for these controllers yet, these bindings
should be considered EXPERIMENTAL for now.
Required properties:
- compatible: Must be one of the following SoC-specific values:
- "renesas,dbsc-r8a73a4" (R-Mobile APE6)
- "renesas,dbsc3-r8a7740" (R-Mobile A1)
- "renesas,sbsc-sh73a0" (SH-Mobile AG5)
- reg: Must contain the base address and length of the memory controller's
registers.
Optional properties:
- interrupts: Must contain a list of interrupt specifiers for memory
controller interrupts, if available.
- interrupt-names: Must contain a list of interrupt names corresponding to
the interrupts in the interrupts property, if available.
Valid interrupt names are:
- "sec" (secure interrupt)
- "temp" (normal (temperature) interrupt)
- power-domains: Must contain a reference to the PM domain that the memory
controller belongs to, if available.
Example:
sbsc1: memory-controller@fe400000 {
compatible = "renesas,sbsc-sh73a0";
reg = <0xfe400000 0x400>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
<0 36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sec", "temp";
power-domains = <&pd_a4bc0>;
};

56
Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml Normal file
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@@ -0,0 +1,56 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas DDR Bus Controllers
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
Renesas SoCs contain one or more memory controllers. These memory
controllers differ from one SoC variant to another, and are called by
different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
(DBSC3)", or "SDRAM Bus State Controller (SBSC)").
properties:
compatible:
enum:
- renesas,dbsc-r8a73a4 # R-Mobile APE6
- renesas,dbsc3-r8a7740 # R-Mobile A1
- renesas,sbsc-sh73a0 # SH-Mobile AG5
reg:
maxItems: 1
interrupts:
maxItems: 2
interrupt-names:
items:
- const: sec # secure interrupt
- const: temp # normal (temperature) interrupt
power-domains:
maxItems: 1
required:
- compatible
- reg
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
sbsc1: memory-controller@fe400000 {
compatible = "renesas,sbsc-sh73a0";
reg = <0xfe400000 0x400>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sec", "temp";
power-domains = <&pd_a4bc0>;
};