Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson:
"New and/or improved SoC support for this release:
Marvell Berlin:
- Enable standard DT-based cpufreq
- Add CPU hotplug support
Freescale:
- Ethernet init for i.MX7D
- Suspend/resume support for i.MX6UL
Allwinner:
- Support for R8 chipset (used on NTC's $9 C.H.I.P board)
Mediatek:
- SMP support for some platforms
Uniphier:
- L2 support
- Cleaned up SMP support, etc.
plus a handful of other patches around above functionality, and a few
other smaller changes"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits)
ARM: uniphier: rework SMP operations to use trampoline code
ARM: uniphier: add outer cache support
Documentation: EXYNOS: Update bootloader interface on exynos542x
ARM: mvebu: add broken-idle option
ARM: orion5x: use mac_pton() helper
ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned
ARM: sunxi: Add R8 support
ARM: digicolor: select pinctrl/gpio driver
arm: berlin: add CPU hotplug support
arm: berlin: use non-self-cleared reset register to reset cpu
ARM: mediatek: add smp bringup code
ARM: mediatek: enable gpt6 on boot up to make arch timer working
soc: mediatek: Fix random hang up issue while kernel init
soc: ti: qmss: make acc queue support optional in the driver
soc: ti: add firmware file name as part of the driver
Documentation: dt: soc: Add description for knav qmss driver
ARM: S3C64XX: Use PWM lookup table for mach-smartq
ARM: S3C64XX: Use PWM lookup table for mach-hmt
ARM: S3C64XX: Use PWM lookup table for mach-crag6410
ARM: S3C64XX: Use PWM lookup table for smdk6410
...
This commit is contained in:
Linus Torvalds
@@ -974,6 +974,16 @@ config CACHE_TAUROS2
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This option enables the Tauros2 L2 cache controller (as
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found on PJ1/PJ4).
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config CACHE_UNIPHIER
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bool "Enable the UniPhier outer cache controller"
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depends on ARCH_UNIPHIER
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default y
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select OUTER_CACHE
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select OUTER_CACHE_SYNC
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help
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This option enables the UniPhier outer cache (system cache)
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controller.
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config CACHE_XSC3L2
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bool "Enable the L2 cache on XScale3"
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depends on CPU_XSC3
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@@ -103,3 +103,4 @@ obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
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obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o l2c-l2x0-resume.o
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obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
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obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o
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obj-$(CONFIG_CACHE_UNIPHIER) += cache-uniphier.o
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555
arch/arm/mm/cache-uniphier.c
Normal file
555
arch/arm/mm/cache-uniphier.c
Normal file
@@ -0,0 +1,555 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "uniphier: " fmt
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/log2.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <asm/hardware/cache-uniphier.h>
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#include <asm/outercache.h>
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/* control registers */
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#define UNIPHIER_SSCC 0x0 /* Control Register */
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#define UNIPHIER_SSCC_BST BIT(20) /* UCWG burst read */
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#define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */
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#define UNIPHIER_SSCC_WTG BIT(18) /* WT gathering on */
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#define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */
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#define UNIPHIER_SSCC_ON BIT(0) /* enable cache */
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#define UNIPHIER_SSCLPDAWCR 0x30 /* Unified/Data Active Way Control */
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#define UNIPHIER_SSCLPIAWCR 0x34 /* Instruction Active Way Control */
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/* revision registers */
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#define UNIPHIER_SSCID 0x0 /* ID Register */
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/* operation registers */
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#define UNIPHIER_SSCOPE 0x244 /* Cache Operation Primitive Entry */
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#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
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#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
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#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
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#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
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#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
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#define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */
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#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
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#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
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#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
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#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
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#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
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#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
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#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
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#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
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#define UNIPHIER_SSCOQM_CE BIT(15) /* notify completion */
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#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
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#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
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#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
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#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
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#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
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#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
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#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
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#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
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#define UNIPHIER_SSCOQAD 0x24c /* Cache Operation Queue Address */
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#define UNIPHIER_SSCOQSZ 0x250 /* Cache Operation Queue Size */
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#define UNIPHIER_SSCOQMASK 0x254 /* Cache Operation Queue Address Mask */
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#define UNIPHIER_SSCOQWN 0x258 /* Cache Operation Queue Way Number */
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#define UNIPHIER_SSCOPPQSEF 0x25c /* Cache Operation Queue Set Complete*/
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#define UNIPHIER_SSCOPPQSEF_FE BIT(1)
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#define UNIPHIER_SSCOPPQSEF_OE BIT(0)
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#define UNIPHIER_SSCOLPQS 0x260 /* Cache Operation Queue Status */
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#define UNIPHIER_SSCOLPQS_EF BIT(2)
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#define UNIPHIER_SSCOLPQS_EST BIT(1)
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#define UNIPHIER_SSCOLPQS_QST BIT(0)
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/* Is the touch/pre-fetch destination specified by ways? */
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#define UNIPHIER_SSCOQM_TID_IS_WAY(op) \
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((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY)
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/* Is the operation region specified by address range? */
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#define UNIPHIER_SSCOQM_S_IS_RANGE(op) \
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((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
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/**
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* uniphier_cache_data - UniPhier outer cache specific data
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*
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* @ctrl_base: virtual base address of control registers
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* @rev_base: virtual base address of revision registers
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* @op_base: virtual base address of operation registers
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* @way_present_mask: each bit specifies if the way is present
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* @way_locked_mask: each bit specifies if the way is locked
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* @nsets: number of associativity sets
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* @line_size: line size in bytes
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* @range_op_max_size: max size that can be handled by a single range operation
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* @list: list node to include this level in the whole cache hierarchy
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*/
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struct uniphier_cache_data {
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void __iomem *ctrl_base;
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void __iomem *rev_base;
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void __iomem *op_base;
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u32 way_present_mask;
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u32 way_locked_mask;
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u32 nsets;
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u32 line_size;
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u32 range_op_max_size;
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struct list_head list;
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};
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/*
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* List of the whole outer cache hierarchy. This list is only modified during
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* the early boot stage, so no mutex is taken for the access to the list.
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*/
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static LIST_HEAD(uniphier_cache_list);
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/**
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* __uniphier_cache_sync - perform a sync point for a particular cache level
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*
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* @data: cache controller specific data
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*/
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static void __uniphier_cache_sync(struct uniphier_cache_data *data)
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{
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/* This sequence need not be atomic. Do not disable IRQ. */
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writel_relaxed(UNIPHIER_SSCOPE_CM_SYNC,
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data->op_base + UNIPHIER_SSCOPE);
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/* need a read back to confirm */
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readl_relaxed(data->op_base + UNIPHIER_SSCOPE);
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}
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/**
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* __uniphier_cache_maint_common - run a queue operation for a particular level
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*
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* @data: cache controller specific data
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* @start: start address of range operation (don't care for "all" operation)
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* @size: data size of range operation (don't care for "all" operation)
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* @operation: flags to specify the desired cache operation
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*/
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static void __uniphier_cache_maint_common(struct uniphier_cache_data *data,
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unsigned long start,
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unsigned long size,
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u32 operation)
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{
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unsigned long flags;
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/*
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* No spin lock is necessary here because:
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*
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* [1] This outer cache controller is able to accept maintenance
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* operations from multiple CPUs at a time in an SMP system; if a
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* maintenance operation is under way and another operation is issued,
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* the new one is stored in the queue. The controller performs one
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* operation after another. If the queue is full, the status register,
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* UNIPHIER_SSCOPPQSEF, indicates that the queue registration has
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* failed. The status registers, UNIPHIER_{SSCOPPQSEF, SSCOLPQS}, have
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* different instances for each CPU, i.e. each CPU can track the status
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* of the maintenance operations triggered by itself.
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*
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* [2] The cache command registers, UNIPHIER_{SSCOQM, SSCOQAD, SSCOQSZ,
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* SSCOQWN}, are shared between multiple CPUs, but the hardware still
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* guarantees the registration sequence is atomic; the write access to
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* them are arbitrated by the hardware. The first accessor to the
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* register, UNIPHIER_SSCOQM, holds the access right and it is released
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* by reading the status register, UNIPHIER_SSCOPPQSEF. While one CPU
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* is holding the access right, other CPUs fail to register operations.
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* One CPU should not hold the access right for a long time, so local
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* IRQs should be disabled while the following sequence.
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*/
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local_irq_save(flags);
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/* clear the complete notification flag */
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writel_relaxed(UNIPHIER_SSCOLPQS_EF, data->op_base + UNIPHIER_SSCOLPQS);
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do {
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/* set cache operation */
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writel_relaxed(UNIPHIER_SSCOQM_CE | operation,
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data->op_base + UNIPHIER_SSCOQM);
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/* set address range if needed */
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if (likely(UNIPHIER_SSCOQM_S_IS_RANGE(operation))) {
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writel_relaxed(start, data->op_base + UNIPHIER_SSCOQAD);
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writel_relaxed(size, data->op_base + UNIPHIER_SSCOQSZ);
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}
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/* set target ways if needed */
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if (unlikely(UNIPHIER_SSCOQM_TID_IS_WAY(operation)))
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writel_relaxed(data->way_locked_mask,
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data->op_base + UNIPHIER_SSCOQWN);
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} while (unlikely(readl_relaxed(data->op_base + UNIPHIER_SSCOPPQSEF) &
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(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
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/* wait until the operation is completed */
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while (likely(readl_relaxed(data->op_base + UNIPHIER_SSCOLPQS) !=
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UNIPHIER_SSCOLPQS_EF))
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cpu_relax();
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local_irq_restore(flags);
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}
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static void __uniphier_cache_maint_all(struct uniphier_cache_data *data,
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u32 operation)
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{
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__uniphier_cache_maint_common(data, 0, 0,
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UNIPHIER_SSCOQM_S_ALL | operation);
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__uniphier_cache_sync(data);
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}
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static void __uniphier_cache_maint_range(struct uniphier_cache_data *data,
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unsigned long start, unsigned long end,
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u32 operation)
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{
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unsigned long size;
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/*
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* If the start address is not aligned,
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* perform a cache operation for the first cache-line
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*/
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start = start & ~(data->line_size - 1);
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size = end - start;
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if (unlikely(size >= (unsigned long)(-data->line_size))) {
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/* this means cache operation for all range */
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__uniphier_cache_maint_all(data, operation);
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return;
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}
|
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|
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/*
|
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* If the end address is not aligned,
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* perform a cache operation for the last cache-line
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*/
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size = ALIGN(size, data->line_size);
|
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|
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while (size) {
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unsigned long chunk_size = min_t(unsigned long, size,
|
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data->range_op_max_size);
|
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|
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__uniphier_cache_maint_common(data, start, chunk_size,
|
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UNIPHIER_SSCOQM_S_RANGE | operation);
|
||||
|
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start += chunk_size;
|
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size -= chunk_size;
|
||||
}
|
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|
||||
__uniphier_cache_sync(data);
|
||||
}
|
||||
|
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static void __uniphier_cache_enable(struct uniphier_cache_data *data, bool on)
|
||||
{
|
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u32 val = 0;
|
||||
|
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if (on)
|
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val = UNIPHIER_SSCC_WTG | UNIPHIER_SSCC_PRD | UNIPHIER_SSCC_ON;
|
||||
|
||||
writel_relaxed(val, data->ctrl_base + UNIPHIER_SSCC);
|
||||
}
|
||||
|
||||
static void __init __uniphier_cache_set_locked_ways(
|
||||
struct uniphier_cache_data *data,
|
||||
u32 way_mask)
|
||||
{
|
||||
data->way_locked_mask = way_mask & data->way_present_mask;
|
||||
|
||||
writel_relaxed(~data->way_locked_mask & data->way_present_mask,
|
||||
data->ctrl_base + UNIPHIER_SSCLPDAWCR);
|
||||
}
|
||||
|
||||
static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
|
||||
u32 operation)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
list_for_each_entry(data, &uniphier_cache_list, list)
|
||||
__uniphier_cache_maint_range(data, start, end, operation);
|
||||
}
|
||||
|
||||
static void uniphier_cache_maint_all(u32 operation)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
list_for_each_entry(data, &uniphier_cache_list, list)
|
||||
__uniphier_cache_maint_all(data, operation);
|
||||
}
|
||||
|
||||
static void uniphier_cache_inv_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV);
|
||||
}
|
||||
|
||||
static void uniphier_cache_clean_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_CLEAN);
|
||||
}
|
||||
|
||||
static void uniphier_cache_flush_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH);
|
||||
}
|
||||
|
||||
static void __init uniphier_cache_inv_all(void)
|
||||
{
|
||||
uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
|
||||
}
|
||||
|
||||
static void uniphier_cache_flush_all(void)
|
||||
{
|
||||
uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
|
||||
}
|
||||
|
||||
static void uniphier_cache_disable(void)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
list_for_each_entry_reverse(data, &uniphier_cache_list, list)
|
||||
__uniphier_cache_enable(data, false);
|
||||
|
||||
uniphier_cache_flush_all();
|
||||
}
|
||||
|
||||
static void __init uniphier_cache_enable(void)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
uniphier_cache_inv_all();
|
||||
|
||||
list_for_each_entry(data, &uniphier_cache_list, list) {
|
||||
__uniphier_cache_enable(data, true);
|
||||
__uniphier_cache_set_locked_ways(data, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void uniphier_cache_sync(void)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
list_for_each_entry(data, &uniphier_cache_list, list)
|
||||
__uniphier_cache_sync(data);
|
||||
}
|
||||
|
||||
int __init uniphier_cache_l2_is_enabled(void)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
data = list_first_entry_or_null(&uniphier_cache_list,
|
||||
struct uniphier_cache_data, list);
|
||||
if (!data)
|
||||
return 0;
|
||||
|
||||
return !!(readl_relaxed(data->ctrl_base + UNIPHIER_SSCC) &
|
||||
UNIPHIER_SSCC_ON);
|
||||
}
|
||||
|
||||
void __init uniphier_cache_l2_touch_range(unsigned long start,
|
||||
unsigned long end)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
data = list_first_entry_or_null(&uniphier_cache_list,
|
||||
struct uniphier_cache_data, list);
|
||||
if (data)
|
||||
__uniphier_cache_maint_range(data, start, end,
|
||||
UNIPHIER_SSCOQM_TID_WAY |
|
||||
UNIPHIER_SSCOQM_CM_TOUCH);
|
||||
}
|
||||
|
||||
void __init uniphier_cache_l2_set_locked_ways(u32 way_mask)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
|
||||
data = list_first_entry_or_null(&uniphier_cache_list,
|
||||
struct uniphier_cache_data, list);
|
||||
if (data)
|
||||
__uniphier_cache_set_locked_ways(data, way_mask);
|
||||
}
|
||||
|
||||
static const struct of_device_id uniphier_cache_match[] __initconst = {
|
||||
{
|
||||
.compatible = "socionext,uniphier-system-cache",
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct device_node * __init uniphier_cache_get_next_level_node(
|
||||
struct device_node *np)
|
||||
{
|
||||
u32 phandle;
|
||||
|
||||
if (of_property_read_u32(np, "next-level-cache", &phandle))
|
||||
return NULL;
|
||||
|
||||
return of_find_node_by_phandle(phandle);
|
||||
}
|
||||
|
||||
static int __init __uniphier_cache_init(struct device_node *np,
|
||||
unsigned int *cache_level)
|
||||
{
|
||||
struct uniphier_cache_data *data;
|
||||
u32 level, cache_size;
|
||||
struct device_node *next_np;
|
||||
int ret = 0;
|
||||
|
||||
if (!of_match_node(uniphier_cache_match, np)) {
|
||||
pr_err("L%d: not compatible with uniphier cache\n",
|
||||
*cache_level);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(np, "cache-level", &level)) {
|
||||
pr_err("L%d: cache-level is not specified\n", *cache_level);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (level != *cache_level) {
|
||||
pr_err("L%d: cache-level is unexpected value %d\n",
|
||||
*cache_level, level);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!of_property_read_bool(np, "cache-unified")) {
|
||||
pr_err("L%d: cache-unified is not specified\n", *cache_level);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
if (of_property_read_u32(np, "cache-line-size", &data->line_size) ||
|
||||
!is_power_of_2(data->line_size)) {
|
||||
pr_err("L%d: cache-line-size is unspecified or invalid\n",
|
||||
*cache_level);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(np, "cache-sets", &data->nsets) ||
|
||||
!is_power_of_2(data->nsets)) {
|
||||
pr_err("L%d: cache-sets is unspecified or invalid\n",
|
||||
*cache_level);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (of_property_read_u32(np, "cache-size", &cache_size) ||
|
||||
cache_size == 0 || cache_size % (data->nsets * data->line_size)) {
|
||||
pr_err("L%d: cache-size is unspecified or invalid\n",
|
||||
*cache_level);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
data->way_present_mask =
|
||||
((u32)1 << cache_size / data->nsets / data->line_size) - 1;
|
||||
|
||||
data->ctrl_base = of_iomap(np, 0);
|
||||
if (!data->ctrl_base) {
|
||||
pr_err("L%d: failed to map control register\n", *cache_level);
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
data->rev_base = of_iomap(np, 1);
|
||||
if (!data->rev_base) {
|
||||
pr_err("L%d: failed to map revision register\n", *cache_level);
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
data->op_base = of_iomap(np, 2);
|
||||
if (!data->op_base) {
|
||||
pr_err("L%d: failed to map operation register\n", *cache_level);
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (*cache_level == 2) {
|
||||
u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
|
||||
/*
|
||||
* The size of range operation is limited to (1 << 22) or less
|
||||
* for PH-sLD8 or older SoCs.
|
||||
*/
|
||||
if (revision <= 0x16)
|
||||
data->range_op_max_size = (u32)1 << 22;
|
||||
}
|
||||
|
||||
data->range_op_max_size -= data->line_size;
|
||||
|
||||
INIT_LIST_HEAD(&data->list);
|
||||
list_add_tail(&data->list, &uniphier_cache_list); /* no mutex */
|
||||
|
||||
/*
|
||||
* OK, this level has been successfully initialized. Look for the next
|
||||
* level cache. Do not roll back even if the initialization of the
|
||||
* next level cache fails because we want to continue with available
|
||||
* cache levels.
|
||||
*/
|
||||
next_np = uniphier_cache_get_next_level_node(np);
|
||||
if (next_np) {
|
||||
(*cache_level)++;
|
||||
ret = __uniphier_cache_init(next_np, cache_level);
|
||||
}
|
||||
of_node_put(next_np);
|
||||
|
||||
return ret;
|
||||
err:
|
||||
iounmap(data->op_base);
|
||||
iounmap(data->rev_base);
|
||||
iounmap(data->ctrl_base);
|
||||
kfree(data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int __init uniphier_cache_init(void)
|
||||
{
|
||||
struct device_node *np = NULL;
|
||||
unsigned int cache_level;
|
||||
int ret = 0;
|
||||
|
||||
/* look for level 2 cache */
|
||||
while ((np = of_find_matching_node(np, uniphier_cache_match)))
|
||||
if (!of_property_read_u32(np, "cache-level", &cache_level) &&
|
||||
cache_level == 2)
|
||||
break;
|
||||
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
ret = __uniphier_cache_init(np, &cache_level);
|
||||
of_node_put(np);
|
||||
|
||||
if (ret) {
|
||||
/*
|
||||
* Error out iif L2 initialization fails. Continue with any
|
||||
* error on L3 or outer because they are optional.
|
||||
*/
|
||||
if (cache_level == 2) {
|
||||
pr_err("failed to initialize L2 cache\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
cache_level--;
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
outer_cache.inv_range = uniphier_cache_inv_range;
|
||||
outer_cache.clean_range = uniphier_cache_clean_range;
|
||||
outer_cache.flush_range = uniphier_cache_flush_range;
|
||||
outer_cache.flush_all = uniphier_cache_flush_all;
|
||||
outer_cache.disable = uniphier_cache_disable;
|
||||
outer_cache.sync = uniphier_cache_sync;
|
||||
|
||||
uniphier_cache_enable();
|
||||
|
||||
pr_info("enabled outer cache (cache level: %d)\n", cache_level);
|
||||
|
||||
return ret;
|
||||
}
|
||||
Reference in New Issue
Block a user