Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
SuperH updates for 3.3 merge window. * tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: (38 commits) sh: magicpanelr2: Update for parse_mtd_partitions() fallout. sh: mach-rsk: Update for parse_mtd_partitions() fallout. sh: sh2a: Improve cache flush/invalidate functions sh: also without PM_RUNTIME pm_runtime.o must be built sh: add a resource name for shdma sh: Remove redundant try_to_freeze() invocations. sh: Ensure IRQs are enabled across do_notify_resume(). sh: Fix up store queue code for subsys_interface changes. sh: clkfwk: sh_clk_init_parent() should be called after clk_register() sh: add platform_device for renesas_usbhs in board-sh7757lcr sh: modify clock-sh7757 for renesas_usbhs sh: pfc: ioremap() support sh: use ioread32/iowrite32 and mapped_reg for div6 sh: use ioread32/iowrite32 and mapped_reg for div4 sh: use ioread32/iowrite32 and mapped_reg for mstp32 sh: extend clock struct with mapped_reg member sh: clkfwk: clock-sh73a0: all div6_clks use SH_CLK_DIV6_EXT() sh: clkfwk: clock-sh7724: all div6_clks use SH_CLK_DIV6_EXT() sh: clock-sh7723: add CLKDEV_ICK_ID for cleanup serial: sh-sci: Handle GPIO function requests. ...
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@@ -49,6 +49,10 @@ enum {
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* SCSPTR, optional */
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#define SCSPTR_RTSIO (1 << 7)
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#define SCSPTR_CTSIO (1 << 5)
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/* Offsets into the sci_port->irqs array */
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enum {
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SCIx_ERI_IRQ,
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@@ -60,6 +64,17 @@ enum {
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SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
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};
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/* Offsets into the sci_port->gpios array */
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enum {
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SCIx_SCK,
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SCIx_RXD,
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SCIx_TXD,
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SCIx_CTS,
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SCIx_RTS,
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SCIx_NR_FNS,
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};
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enum {
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SCIx_PROBE_REGTYPE,
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@@ -108,14 +123,21 @@ struct plat_sci_port_ops {
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void (*init_pins)(struct uart_port *, unsigned int cflag);
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};
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/*
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* Port-specific capabilities
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*/
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#define SCIx_HAVE_RTSCTS (1 << 0)
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/*
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* Platform device specific platform_data struct
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*/
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struct plat_sci_port {
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unsigned long mapbase; /* resource base */
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unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
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unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */
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unsigned int type; /* SCI / SCIF / IRDA */
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upf_t flags; /* UPF_* flags */
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unsigned long capabilities; /* Port features/capabilities */
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unsigned int scbrr_algo_id; /* SCBRR calculation algo */
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unsigned int scscr; /* SCSCR initialization */
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@@ -49,6 +49,7 @@ struct clk {
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void __iomem *enable_reg;
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unsigned int enable_bit;
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void __iomem *mapped_reg;
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unsigned long arch_flags;
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void *priv;
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@@ -131,10 +132,9 @@ int sh_clk_div4_enable_register(struct clk *clks, int nr,
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int sh_clk_div4_reparent_register(struct clk *clks, int nr,
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struct clk_div4_table *table);
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#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \
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#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \
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_num_parents, _src_shift, _src_width) \
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{ \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_reg, \
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.flags = _flags, \
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.parent_table = _parents, \
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@@ -144,7 +144,11 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
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}
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#define SH_CLK_DIV6(_parent, _reg, _flags) \
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SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)
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{ \
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.parent = _parent, \
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.enable_reg = (void __iomem *)_reg, \
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.flags = _flags, \
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}
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int sh_clk_div6_register(struct clk *clks, int nr);
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int sh_clk_div6_reparent_register(struct clk *clks, int nr);
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@@ -55,6 +55,7 @@ struct pinmux_cfg_reg {
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struct pinmux_data_reg {
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unsigned long reg, reg_width, reg_shadow;
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pinmux_enum_t *enum_ids;
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void __iomem *mapped_reg;
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};
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#define PINMUX_DATA_REG(name, r, r_width) \
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@@ -75,6 +76,12 @@ struct pinmux_range {
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pinmux_enum_t force;
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};
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struct pfc_window {
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phys_addr_t phys;
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void __iomem *virt;
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unsigned long size;
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};
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struct pinmux_info {
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char *name;
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pinmux_enum_t reserved_id;
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@@ -98,6 +105,10 @@ struct pinmux_info {
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struct pinmux_irq *gpio_irq;
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unsigned int gpio_irq_size;
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struct resource *resource;
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unsigned int num_resources;
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struct pfc_window *window;
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struct gpio_chip chip;
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};
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