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Merge branch 'next-s3c64xx-device' into next-merged

Browse Source 
Conflicts:

	arch/arm/mach-s3c2440/mach-at2440evb.c
This commit is contained in:
Ben Dooks
2008-12-18 16:17:37 +00:00
parent 7f2754378f 438a5d42e0
commit 56c035c9ce
81 changed files with 4027 additions and 218 deletions
Download Patch File Download Diff File Expand all files Collapse all files

70
arch/arm/plat-s3c/Kconfig
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@@ -110,3 +110,73 @@ config S3C_LOWLEVEL_UART_PORT
such as the `Uncompressing...` at start time. The value of
this configuration should be between zero and two. The port
must have been initialised by the boot-loader before use.
# options for gpiolib support
config S3C_GPIO_SPACE
int "Space between gpio banks"
default 0
help
Add a number of spare GPIO entries between each bank for debugging
purposes. This allows any problems where an counter overflows from
one bank to another to be caught, at the expense of using a little
more memory.
config S3C_GPIO_TRACK
bool
help
Internal configuration option to enable the s3c specific gpio
chip tracking if the platform requires it.
config S3C_GPIO_PULL_UPDOWN
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_PULL_DOWN
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_PULL_UP
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_CFG_S3C24XX
bool
help
Internal configuration to enable S3C24XX style GPIO configuration
functions.
config S3C_GPIO_CFG_S3C64XX
bool
help
Internal configuration to enable S3C64XX style GPIO configuration
functions.
# device definitions to compile in
config S3C_DEV_HSMMC
bool
depends on PLAT_S3C
help
Compile in platform device definitions for HSMMC code
config S3C_DEV_HSMMC1
bool
depends on PLAT_S3C
help
Compile in platform device definitions for HSMMC channel 1
config S3C_DEV_I2C1
bool
depends on PLAT_S3C
help
Compile in platform device definitions for I2C channel 1
config S3C_DEV_FB
bool
depends on PLAT_S3C
help
Compile in platform device definition for framebuffer

12
arch/arm/plat-s3c/Makefile
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@@ -14,4 +14,14 @@ obj- :=
obj-y += init.o
obj-y += time.o
obj-y += clock.o
obj-y += pwm-clock.o
obj-y += pwm-clock.o
obj-y += gpio.o
obj-y += gpio-config.o
# devices
obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o

72
arch/arm/plat-s3c/dev-fb.c Normal file
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@@ -0,0 +1,72 @@
/* linux/arch/arm/plat-s3c/dev-fb.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for framebuffer device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <mach/map.h>
#include <mach/regs-fb.h>
#include <plat/fb.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_fb_resource[] = {
[0] = {
.start = S3C_PA_FB,
.end = S3C_PA_FB + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCD_VSYNC,
.end = IRQ_LCD_VSYNC,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_LCD_FIFO,
.end = IRQ_LCD_FIFO,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_LCD_SYSTEM,
.end = IRQ_LCD_SYSTEM,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_fb = {
.name = "s3c-fb",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_fb_resource),
.resource = s3c_fb_resource,
.dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask,
.dev.coherent_dma_mask = 0xffffffffUL,
};
void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
{
struct s3c_fb_platdata *npd;
if (!pd) {
printk(KERN_ERR "%s: no platform data\n", __func__);
return;
}
npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
s3c_device_fb.dev.platform_data = npd;
}

68
arch/arm/plat-s3c/dev-hsmmc.c Normal file
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@@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-hsmmc.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for hsmmc devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc_resource[] = {
[0] = {
.start = S3C_PA_HSMMC0,
.end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC0,
.end = IRQ_HSMMC0,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc0 = {
.name = "s3c-sdhci",
.id = 0,
.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
.resource = s3c_hsmmc_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc0_def_platdata,
},
};
void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}

68
arch/arm/plat-s3c/dev-hsmmc1.c Normal file
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@@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for hsmmc device 1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc1_resource[] = {
[0] = {
.start = S3C_PA_HSMMC1,
.end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC1,
.end = IRQ_HSMMC1,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc1 = {
.name = "s3c-sdhci",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
.resource = s3c_hsmmc1_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc1_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc1_def_platdata,
},
};
void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}

71
arch/arm/plat-s3c/dev-i2c0.c Normal file
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@@ -0,0 +1,71 @@
/* linux/arch/arm/plat-s3c/dev-i2c0.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for i2c device 0
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/regs-iic.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C_PA_IIC,
.end = S3C_PA_IIC + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC,
.end = IRQ_IIC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_i2c0 = {
.name = "s3c2410-i2c",
#ifdef CONFIG_S3C_DEV_I2C1
.id = 0,
#else
.id = -1,
#endif
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
.flags = 0,
.slave_addr = 0x10,
.bus_freq = 100*1000,
.max_freq = 400*1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd)
pd = &default_i2c_data0;
npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
else if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c0_cfg_gpio;
s3c_device_i2c0.dev.platform_data = npd;
}

68
arch/arm/plat-s3c/dev-i2c1.c Normal file
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@@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-i2c1.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for i2c device 1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/regs-iic.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C_PA_IIC1,
.end = S3C_PA_IIC1 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC1,
.end = IRQ_IIC1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_i2c1 = {
.name = "s3c2410-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
.flags = 0,
.bus_num = 1,
.slave_addr = 0x10,
.bus_freq = 100*1000,
.max_freq = 400*1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd)
pd = &default_i2c_data1;
npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
else if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c1_cfg_gpio;
s3c_device_i2c1.dev.platform_data = npd;
}

163
arch/arm/plat-s3c/gpio-config.c Normal file
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@@ -0,0 +1,163 @@
/* linux/arch/arm/plat-s3c/gpio-config.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series GPIO configuration core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long flags;
int offset;
int ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
local_irq_save(flags);
ret = s3c_gpio_do_setcfg(chip, offset, config);
local_irq_restore(flags);
return ret;
}
int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long flags;
int offset, ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
local_irq_save(flags);
ret = s3c_gpio_do_setpull(chip, offset, pull);
local_irq_restore(flags);
return ret;
}
#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off;
u32 con;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
/* Map output to 0, and SFN2 to 1 */
cfg -= 1;
if (cfg > 1)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x1 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off * 2;
u32 con;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
if (cfg > 3)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x3 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
#endif
#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = (off & 7) * 4;
u32 con;
if (off < 8 && chip->chip.ngpio >= 8)
reg -= 4;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0xf << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup;
pup = __raw_readl(reg);
pup &= ~(3 << shift);
pup |= pull << shift;
__raw_writel(pup, reg);
return 0;
}
s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
unsigned int off)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup = __raw_readl(reg);
pup >>= shift;
pup &= 0x3;
return (__force s3c_gpio_pull_t)pup;
}
#endif

147
arch/arm/plat-s3c/gpio.c Normal file
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@@ -0,0 +1,147 @@
/* linux/arch/arm/plat-s3c/gpio.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series GPIO core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/gpio-core.h>
#ifdef CONFIG_S3C_GPIO_TRACK
struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
{
unsigned int gpn;
int i;
gpn = chip->chip.base;
for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
BUG_ON(gpn > ARRAY_SIZE(s3c_gpios));
s3c_gpios[gpn] = chip;
}
}
#endif /* CONFIG_S3C_GPIO_TRACK */
/* Default routines for controlling GPIO, based on the original S3C24XX
* GPIO functions which deal with the case where each gpio bank of the
* chip is as following:
*
* base + 0x00: Control register, 2 bits per gpio
* gpio n: 2 bits starting at (2*n)
* 00 = input, 01 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*/
static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long con;
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
return 0;
}
static int s3c_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
unsigned long con;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= 1 << (offset * 2);
__raw_writel(con, base + 0x00);
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
return 0;
}
static void s3c_gpiolib_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
unsigned long val;
val = __raw_readl(ourchip->base + 0x04);
val >>= offset;
val &= 1;
return val;
}
__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
{
struct gpio_chip *gc = &chip->chip;
int ret;
BUG_ON(!chip->base);
BUG_ON(!gc->label);
BUG_ON(!gc->ngpio);
if (!gc->direction_input)
gc->direction_input = s3c_gpiolib_input;
if (!gc->direction_output)
gc->direction_output = s3c_gpiolib_output;
if (!gc->set)
gc->set = s3c_gpiolib_set;
if (!gc->get)
gc->get = s3c_gpiolib_get;
/* gpiochip_add() prints own failure message on error. */
ret = gpiochip_add(gc);
if (ret >= 0)
s3c_gpiolib_track(chip);
}

8
arch/arm/plat-s3c/include/plat/devs.h
View File

@@ -24,15 +24,19 @@ extern struct platform_device *s3c24xx_uart_src[];
extern struct platform_device s3c_device_timer[];
extern struct platform_device s3c_device_fb;
extern struct platform_device s3c_device_usb;
extern struct platform_device s3c_device_lcd;
extern struct platform_device s3c_device_wdt;
extern struct platform_device s3c_device_i2c;
extern struct platform_device s3c_device_i2c0;
extern struct platform_device s3c_device_i2c1;
extern struct platform_device s3c_device_iis;
extern struct platform_device s3c_device_rtc;
extern struct platform_device s3c_device_adc;
extern struct platform_device s3c_device_sdi;
extern struct platform_device s3c_device_hsmmc;
extern struct platform_device s3c_device_hsmmc0;
extern struct platform_device s3c_device_hsmmc1;
extern struct platform_device s3c_device_hsmmc2;
extern struct platform_device s3c_device_spi0;
extern struct platform_device s3c_device_spi1;

73
arch/arm/plat-s3c/include/plat/fb.h Normal file
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/* linux/arch/arm/plat-s3c/include/plat/fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - FB platform data definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_FB_H
#define __PLAT_S3C_FB_H __FILE__
/**
* struct s3c_fb_pd_win - per window setup data
* @win_mode: The display parameters to initialise (not for window 0)
* @virtual_x: The virtual X size.
* @virtual_y: The virtual Y size.
*/
struct s3c_fb_pd_win {
struct fb_videomode win_mode;
unsigned short default_bpp;
unsigned short max_bpp;
unsigned short virtual_x;
unsigned short virtual_y;
};
/**
* struct s3c_fb_platdata - S3C driver platform specific information
* @setup_gpio: Setup the external GPIO pins to the right state to transfer
* the data from the display system to the connected display
* device.
* @vidcon0: The base vidcon0 values to control the panel data format.
* @vidcon1: The base vidcon1 values to control the panel data output.
* @win: The setup data for each hardware window, or NULL for unused.
* @display_mode: The LCD output display mode.
*
* The platform data supplies the video driver with all the information
* it requires to work with the display(s) attached to the machine. It
* controls the initial mode, the number of display windows (0 is always
* the base framebuffer) that are initialised etc.
*
*/
struct s3c_fb_platdata {
void (*setup_gpio)(void);
struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
u32 vidcon0;
u32 vidcon1;
};
/**
* s3c_fb_set_platdata() - Setup the FB device with platform data.
* @pd: The platform data to set. The data is copied from the passed structure
* so the machine data can mark the data __initdata so that any unused
* machines will end up dumping their data at runtime.
*/
extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
/**
* s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface.
*/
extern void s3c64xx_fb_gpio_setup_24bpp(void);
#endif /* __PLAT_S3C_FB_H */

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arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h Normal file
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/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO pin configuration helper definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This is meant for core cpu support, machine or other driver files
* should not be including this header.
*/
#ifndef __PLAT_GPIO_CFG_HELPERS_H
#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
/* As a note, all gpio configuration functions are entered exclusively, either
* with the relevant lock held or the system prevented from doing anything else
* by disabling interrupts.
*/
static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int config)
{
return (chip->config->set_config)(chip, off, config);
}
static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
return (chip->config->set_pull)(chip, off, pull);
}
/**
* s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register
* has two bits of configuration per gpio, which have the following
* functions:
* 00 = input
* 01 = output
* 1x = special function
*/
extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/**
* s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register
* has one bit of configuration for the gpio, where setting the bit
* means the pin is in special function mode and unset means output.
*/
extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/**
* s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register has 4 bits
* of control per GPIO, generally in the form of:
* 0000 = Input
* 0001 = Output
* others = Special functions (dependant on bank)
*
* Note, since the code to deal with the case where there are two control
* registers instead of one, we do not have a seperate set of functions for
* each case.
*/
extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/* Pull-{up,down} resistor controls.
*
* S3C2410,S3C2440,S3C24A0 = Pull-UP,
* S3C2412,S3C2413 = Pull-Down
* S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
* S3C2443 = Pull-Both [not same as S3C6400]
*/
/**
* s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with one
* bit configuring the presence of a pull-up resistor.
*/
extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
* @chip: The gpio chip that is being configured
* @off: The offset for the GPIO being configured
* @param: pull: The pull mode being requested
*
* This is a helper function for the case where we have GPIOs with one
* bit configuring the presence of a pull-down resistor.
*/
extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with two
* bits configuring the presence of a pull resistor, in the following
* order:
* 00 = No pull resistor connected
* 01 = Pull-up resistor connected
* 10 = Pull-down resistor connected
*/
extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
* @chip: The gpio chip that the GPIO pin belongs to
* @off: The offset to the pin to get the configuration of.
*
* This helper function reads the state of the pull-{up,down} resistor for the
* given GPIO in the same case as s3c_gpio_setpull_upown.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
unsigned int off);
/**
* s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with two
* bits configuring the presence of a pull resistor, in the following
* order:
* 00 = Pull-up resistor connected
* 10 = Pull-down resistor connected
* x1 = No pull up resistor
*/
extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
* @chip: The gpio chip that the GPIO pin belongs to.
* @off: The offset to the pin to get the configuration of.
*
* This helper function reads the state of the pull-{up,down} resistor for the
* given GPIO in the same case as s3c_gpio_setpull_upown.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off);
#endif /* __PLAT_GPIO_CFG_HELPERS_H */

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arch/arm/plat-s3c/include/plat/gpio-cfg.h Normal file
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/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO pin configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This file contains the necessary definitions to get the basic gpio
* pin configuration done such as setting a pin to input or output or
* changing the pull-{up,down} configurations.
*/
/* Note, this interface is being added to the s3c64xx arch first and will
* be added to the s3c24xx systems later.
*/
#ifndef __PLAT_GPIO_CFG_H
#define __PLAT_GPIO_CFG_H __FILE__
typedef unsigned int __bitwise__ s3c_gpio_pull_t;
/* forward declaration if gpio-core.h hasn't been included */
struct s3c_gpio_chip;
/**
* struct s3c_gpio_cfg GPIO configuration
* @cfg_eint: Configuration setting when used for external interrupt source
* @get_pull: Read the current pull configuration for the GPIO
* @set_pull: Set the current pull configuraiton for the GPIO
* @set_config: Set the current configuration for the GPIO
* @get_config: Read the current configuration for the GPIO
*
* Each chip can have more than one type of GPIO bank available and some
* have different capabilites even when they have the same control register
* layouts. Provide an point to vector control routine and provide any
* per-bank configuration information that other systems such as the
* external interrupt code will need.
*/
struct s3c_gpio_cfg {
unsigned int cfg_eint;
s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
s3c_gpio_pull_t pull);
unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
unsigned config);
};
#define S3C_GPIO_SPECIAL_MARK (0xfffffff0)
#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x))
/* Defines for generic pin configurations */
#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
#define s3c_gpio_is_cfg_special(_cfg) \
(((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
/**
* s3c_gpio_cfgpin() - Change the GPIO function of a pin.
* @pin pin The pin number to configure.
* @pin to The configuration for the pin's function.
*
* Configure which function is actually connected to the external
* pin, such as an gpio input, output or some form of special function
* connected to an internal peripheral block.
*/
extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
/* Define values for the pull-{up,down} available for each gpio pin.
*
* These values control the state of the weak pull-{up,down} resistors
* available on most pins on the S3C series. Not all chips support both
* up or down settings, and it may be dependant on the chip that is being
* used to whether the particular mode is available.
*/
#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00)
#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01)
#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02)
/**
* s3c_gpio_setpull() - set the state of a gpio pin pull resistor
* @pin: The pin number to configure the pull resistor.
* @pull: The configuration for the pull resistor.
*
* This function sets the state of the pull-{up,down} resistor for the
* specified pin. It will return 0 if successfull, or a negative error
* code if the pin cannot support the requested pull setting.
*/
extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull() - get the pull resistor state of a gpio pin
* @pin: The pin number to get the settings for
*
* Read the pull resistor value for the specified pin.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
#endif /* __PLAT_GPIO_CFG_H */

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arch/arm/plat-s3c/include/plat/gpio-core.h Normal file
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/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
*
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Define the core gpiolib support functions that the s3c platforms may
* need to extend or change depending on the hardware and the s3c chip
* selected at build or found at run time.
*
* These definitions are not intended for driver inclusion, there is
* nothing here that should not live outside the platform and core
* specific code.
*/
struct s3c_gpio_cfg;
/**
* struct s3c_gpio_chip - wrapper for specific implementation of gpio
* @chip: The chip structure to be exported via gpiolib.
* @base: The base pointer to the gpio configuration registers.
* @config: special function and pull-resistor control information.
*
* This wrapper provides the necessary information for the Samsung
* specific gpios being registered with gpiolib.
*/
struct s3c_gpio_chip {
struct gpio_chip chip;
struct s3c_gpio_cfg *config;
void __iomem *base;
};
static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
{
return container_of(gpc, struct s3c_gpio_chip, chip);
}
/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
* @chip: The chip to register
*
* This is a wrapper to gpiochip_add() that takes our specific gpio chip
* information and makes the necessary alterations for the platform and
* notes the information for use with the configuration systems and any
* other parts of the system.
*/
extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
* for use with the configuration calls, and other parts of the s3c gpiolib
* support code.
*
* Not all s3c support code will need this, as some configurations of cpu
* may only support one or two different configuration options and have an
* easy gpio to s3c_gpio_chip mapping function. If this is the case, then
* the machine support file should provide its own s3c_gpiolib_getchip()
* and any other necessary functions.
*/
#ifdef CONFIG_S3C_GPIO_TRACK
extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
{
return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
}
#else
/* machine specific code should provide s3c_gpiolib_getchip */
static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
#endif

35
arch/arm/plat-s3c/include/plat/iic-core.h Normal file
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/* arch/arm/mach-s3c2410/include/mach/iic-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - I2C Controller core functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IIC_CORE_H
#define __ASM_ARCH_IIC_CORE_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
*/
/* re-define device name depending on support. */
static inline void s3c_i2c0_setname(char *name)
{
/* currently this device is always compiled in */
s3c_device_i2c0.name = name;
}
static inline void s3c_i2c1_setname(char *name)
{
#ifdef CONFIG_S3C_DEV_I2C1
s3c_device_i2c1.name = name;
#endif
}
#endif /* __ASM_ARCH_IIC_H */

24
arch/arm/plat-s3c/include/plat/iic.h
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@@ -28,6 +28,30 @@ struct s3c2410_platform_i2c {
unsigned long max_freq; /* max frequency for the bus */
unsigned long min_freq; /* min frequency for the bus */
unsigned int sda_delay; /* pclks (s3c2440 only) */
void (*cfg_gpio)(struct platform_device *dev);
};
/**
* s3c_i2c0_set_platdata - set platform data for i2c0 device
* @i2c: The platform data to set, or NULL for default data.
*
* Register the given platform data for use with the i2c0 device. This
* call copies the platform data, so the caller can use __initdata for
* their copy.
*
* This call will set cfg_gpio if is null to the default platform
* implementation.
*
* Any user of s3c_device_i2c0 should call this, even if it is with
* NULL to ensure that the device is given the default platform data
* as the driver will no longer carry defaults.
*/
extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
/* defined by architecture to configure gpio */
extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
#endif /* __ASM_ARCH_IIC_H */

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arch/arm/plat-s3c/include/plat/regs-fb.h Normal file
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/* arch/arm/plat-s3c/include/plat/regs-fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - new-style framebuffer register definitions
*
* This is the register set for the new style framebuffer interface
* found from the S3C2443 onwards into the S3C2416, S3C2450 and the
* S3C64XX series such as the S3C6400 and S3C6410.
*
* The file does not contain the cpu specific items which are based on
* whichever architecture is selected, it only contains the core of the
* register set. See <mach/regs-fb.h> to get the specifics.
*
* Note, we changed to using regs-fb.h as it avoids any clashes with
* the original regs-lcd.h so out of the way of regs-lcd.h as well as
* indicating the newer block is much more than just an LCD interface.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Please do not include this file directly, use <mach/regs-fb.h> to
* ensure all the localised SoC support is included as necessary.
*/
/* VIDCON0 */
#define VIDCON0 (0x00)
#define VIDCON0_INTERLACE (1 << 29)
#define VIDCON0_VIDOUT_MASK (0x3 << 26)
#define VIDCON0_VIDOUT_SHIFT (26)
#define VIDCON0_VIDOUT_RGB (0x0 << 26)
#define VIDCON0_VIDOUT_TV (0x1 << 26)
#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
#define VIDCON0_L1_DATA_MASK (0x7 << 23)
#define VIDCON0_L1_DATA_SHIFT (23)
#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
#define VIDCON0_L0_DATA_MASK (0x7 << 20)
#define VIDCON0_L0_DATA_SHIFT (20)
#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
#define VIDCON0_PNRMODE_MASK (0x3 << 17)
#define VIDCON0_PNRMODE_SHIFT (17)
#define VIDCON0_PNRMODE_RGB (0x0 << 17)
#define VIDCON0_PNRMODE_BGR (0x1 << 17)
#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
#define VIDCON0_CLKVALUP (1 << 16)
#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
#define VIDCON0_CLKVAL_F_SHIFT (6)
#define VIDCON0_CLKVAL_F_LIMIT (0xff)
#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
#define VIDCON0_VLCKFREE (1 << 5)
#define VIDCON0_CLKDIR (1 << 4)
#define VIDCON0_CLKSEL_MASK (0x3 << 2)
#define VIDCON0_CLKSEL_SHIFT (2)
#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
#define VIDCON0_CLKSEL_LCD (0x1 << 2)
#define VIDCON0_CLKSEL_27M (0x3 << 2)
#define VIDCON0_ENVID (1 << 1)
#define VIDCON0_ENVID_F (1 << 0)
#define VIDCON1 (0x04)
#define VIDCON1_LINECNT_MASK (0x7ff << 16)
#define VIDCON1_LINECNT_SHIFT (16)
#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
#define VIDCON1_VSTATUS_MASK (0x3 << 13)
#define VIDCON1_VSTATUS_SHIFT (13)
#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
#define VIDCON1_INV_VCLK (1 << 7)
#define VIDCON1_INV_HSYNC (1 << 6)
#define VIDCON1_INV_VSYNC (1 << 5)
#define VIDCON1_INV_VDEN (1 << 4)
/* VIDCON2 */
#define VIDCON2 (0x08)
#define VIDCON2_EN601 (1 << 23)
#define VIDCON2_TVFMTSEL_SW (1 << 14)
#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
#define VIDCON2_TVFMTSEL1_SHIFT (12)
#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
#define VIDCON2_ORGYCbCr (1 << 8)
#define VIDCON2_YUVORDCrCb (1 << 7)
/* VIDTCON0 */
#define VIDTCON0_VBPDE_MASK (0xff << 24)
#define VIDTCON0_VBPDE_SHIFT (24)
#define VIDTCON0_VBPDE_LIMIT (0xff)
#define VIDTCON0_VBPDE(_x) ((_x) << 24)
#define VIDTCON0_VBPD_MASK (0xff << 16)
#define VIDTCON0_VBPD_SHIFT (16)
#define VIDTCON0_VBPD_LIMIT (0xff)
#define VIDTCON0_VBPD(_x) ((_x) << 16)
#define VIDTCON0_VFPD_MASK (0xff << 8)
#define VIDTCON0_VFPD_SHIFT (8)
#define VIDTCON0_VFPD_LIMIT (0xff)
#define VIDTCON0_VFPD(_x) ((_x) << 8)
#define VIDTCON0_VSPW_MASK (0xff << 0)
#define VIDTCON0_VSPW_SHIFT (0)
#define VIDTCON0_VSPW_LIMIT (0xff)
#define VIDTCON0_VSPW(_x) ((_x) << 0)
/* VIDTCON1 */
#define VIDTCON1_VFPDE_MASK (0xff << 24)
#define VIDTCON1_VFPDE_SHIFT (24)
#define VIDTCON1_VFPDE_LIMIT (0xff)
#define VIDTCON1_VFPDE(_x) ((_x) << 24)
#define VIDTCON1_HBPD_MASK (0xff << 16)
#define VIDTCON1_HBPD_SHIFT (16)
#define VIDTCON1_HBPD_LIMIT (0xff)
#define VIDTCON1_HBPD(_x) ((_x) << 16)
#define VIDTCON1_HFPD_MASK (0xff << 8)
#define VIDTCON1_HFPD_SHIFT (8)
#define VIDTCON1_HFPD_LIMIT (0xff)
#define VIDTCON1_HFPD(_x) ((_x) << 8)
#define VIDTCON1_HSPW_MASK (0xff << 0)
#define VIDTCON1_HSPW_SHIFT (0)
#define VIDTCON1_HSPW_LIMIT (0xff)
#define VIDTCON1_HSPW(_x) ((_x) << 0)
#define VIDTCON2 (0x18)
#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
#define VIDTCON2_LINEVAL_SHIFT (11)
#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
#define VIDTCON2_LINEVAL(_x) ((_x) << 11)
#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
#define VIDTCON2_HOZVAL_SHIFT (0)
#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
#define VIDTCON2_HOZVAL(_x) ((_x) << 0)
/* WINCONx */
#define WINCONx_BITSWP (1 << 18)
#define WINCONx_BYTSWP (1 << 17)
#define WINCONx_HAWSWP (1 << 16)
#define WINCONx_BURSTLEN_MASK (0x3 << 9)
#define WINCONx_BURSTLEN_SHIFT (9)
#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
#define WINCONx_ENWIN (1 << 0)
#define WINCON0_BPPMODE_MASK (0xf << 2)
#define WINCON0_BPPMODE_SHIFT (2)
#define WINCON0_BPPMODE_1BPP (0x0 << 2)
#define WINCON0_BPPMODE_2BPP (0x1 << 2)
#define WINCON0_BPPMODE_4BPP (0x2 << 2)
#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BLD_PIX (1 << 6)
#define WINCON1_ALPHA_SEL (1 << 1)
#define WINCON1_BPPMODE_MASK (0xf << 2)
#define WINCON1_BPPMODE_SHIFT (2)
#define WINCON1_BPPMODE_1BPP (0x0 << 2)
#define WINCON1_BPPMODE_2BPP (0x1 << 2)
#define WINCON1_BPPMODE_4BPP (0x2 << 2)
#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)
#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)
#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)
#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)
/* For VIDOSD[1..4]C */
#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
#define VIDISD14C_ALPHA0_G_SHIFT (16)
#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
#define VIDISD14C_ALPHA0_B_SHIFT (12)
#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
#define VIDISD14C_ALPHA1_R_SHIFT (8)
#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
#define VIDISD14C_ALPHA1_G_SHIFT (4)
#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
#define VIDISD14C_ALPHA1_B_SHIFT (0)
#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)
#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)
/* Interrupt controls and status */
#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
#define VIDINTCON0_INT_I80IFDONE (1 << 17)
#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
#define VIDINTCON0_FRAMESEL0_SHIFT (15)
#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
#define VIDINTCON0_FRAMESEL1 (1 << 14)
#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14)
#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14)
#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14)
#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14)
#define VIDINTCON0_INT_FRAME (1 << 12)
#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
#define VIDINTCON0_FIFIOSEL_SHIFT (5)
#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
#define VIDINTCON0_INT_FIFO_SHIFT (0)
#define VIDINTCON0_INT_ENABLE (1 << 0)
#define VIDINTCON1 (0x134)
#define VIDINTCON1_INT_I180 (1 << 2)
#define VIDINTCON1_INT_FRAME (1 << 1)
#define VIDINTCON1_INT_FIFO (1 << 0)
/* Window colour-key control registers */
#define WxKEYCON0_KEYBL_EN (1 << 26)
#define WxKEYCON0_KEYEN_F (1 << 25)
#define WxKEYCON0_DIRCON (1 << 24)
#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
#define WxKEYCON0_COMPKEY_SHIFT (0)
#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
#define WxKEYCON1_COLVAL_SHIFT (0)
#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
/* Window blanking (MAP) */
#define WINxMAP_MAP (1 << 24)
#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
#define WINxMAP_MAP_COLOUR_SHIFT (0)
#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
#define WPALCON_PAL_UPDATE (1 << 9)
#define WPALCON_W1PAL_MASK (0x7 << 3)
#define WPALCON_W1PAL_SHIFT (3)
#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
#define WPALCON_W1PAL_24BPP (0x1 << 3)
#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
#define WPALCON_W1PAL_18BPP (0x4 << 3)
#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
#define WPALCON_W0PAL_MASK (0x7 << 0)
#define WPALCON_W0PAL_SHIFT (0)
#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
#define WPALCON_W0PAL_24BPP (0x1 << 0)
#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
#define WPALCON_W0PAL_18BPP (0x4 << 0)
#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)

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/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - SDHCI (HSMMC) register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_SDHCI_REGS_H
#define __PLAT_S3C_SDHCI_REGS_H __FILE__
#define S3C_SDHCI_CONTROL2 (0x80)
#define S3C_SDHCI_CONTROL3 (0x84)
#define S3C64XX_SDHCI_CONTROL4 (0x8C)
#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
#endif /* __PLAT_S3C_SDHCI_REGS_H */

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/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - SDHCI (HSMMC) platform data definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_SDHCI_H
#define __PLAT_S3C_SDHCI_H __FILE__
struct platform_device;
struct mmc_host;
struct mmc_card;
struct mmc_ios;
/**
* struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
* @max_width: The maximum number of data bits supported.
* @host_caps: Standard MMC host capabilities bit field.
* @cfg_gpio: Configure the GPIO for a specific card bit-width
* @cfg_card: Configure the interface for a specific card and speed. This
* is necessary the controllers and/or GPIO blocks require the
* changing of driver-strength and other controls dependant on
* the card and speed of operation.
*
* Initialisation data specific to either the machine or the platform
* for the device driver to use or call-back when configuring gpio or
* card speed information.
*/
struct s3c_sdhci_platdata {
unsigned int max_width;
unsigned int host_caps;
char **clocks; /* set of clock sources */
void (*cfg_gpio)(struct platform_device *dev, int width);
void (*cfg_card)(struct platform_device *dev,
void __iomem *regbase,
struct mmc_ios *ios,
struct mmc_card *card);
};
/**
* s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
* @pd: Platform data to register to device.
*
* Register the given platform data for use withe S3C SDHCI device.
* The call will copy the platform data, so the board definitions can
* make the structure itself __initdata.
*/
extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
/* Default platform data, exported so that per-cpu initialisation can
* set the correct one when there are more than one cpu type selected.
*/
extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
/* Helper function availablity */
#ifdef CONFIG_S3C6410_SETUP_SDHCI
extern char *s3c6410_hsmmc_clksrcs[4];
extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card);
#ifdef CONFIG_S3C_DEV_HSMMC
static inline void s3c6410_default_sdhci0(void)
{
s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
static inline void s3c6410_default_sdhci0(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC1
static inline void s3c6410_default_sdhci1(void)
{
s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC1 */
#else
static inline void s3c6410_default_sdhci0(void) { }
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C6410_SETUP_SDHCI */
#endif /* __PLAT_S3C_SDHCI_H */