Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"Boston platform support:
- Document DT bindings
- Add CLK driver for board clocks
CM:
- Avoid per-core locking with CM3 & higher
- WARN on attempt to lock invalid VP, not BUG
CPS:
- Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6
- Prevent multi-core with dcache aliasing
- Handle cores not powering down more gracefully
- Handle spurious VP starts more gracefully
DSP:
- Add lwx & lhx missaligned access support
eBPF:
- Add MIPS support along with many supporting change to add the
required infrastructure
Generic arch code:
- Misc sysmips MIPS_ATOMIC_SET fixes
- Drop duplicate HAVE_SYSCALL_TRACEPOINTS
- Negate error syscall return in trace
- Correct forced syscall errors
- Traced negative syscalls should return -ENOSYS
- Allow samples/bpf/tracex5 to access syscall arguments for sane
traces
- Cleanup from old Kconfig options in defconfigs
- Fix PREF instruction usage by memcpy for MIPS R6
- Fix various special cases in the FPU eulation
- Fix some special cases in MIPS16e2 support
- Fix MIPS I ISA /proc/cpuinfo reporting
- Sort MIPS Kconfig alphabetically
- Fix minimum alignment requirement of IRQ stack as required by
ABI / GCC
- Fix special cases in the module loader
- Perform post-DMA cache flushes on systems with MAARs
- Probe the I6500 CPU
- Cleanup cmpxchg and add support for 1 and 2 byte operations
- Use queued read/write locks (qrwlock)
- Use queued spinlocks (qspinlock)
- Add CPU shared FTLB feature detection
- Handle tlbex-tlbp race condition
- Allow storing pgd in C0_CONTEXT for MIPSr6
- Use current_cpu_type() in m4kc_tlbp_war()
- Support Boston in the generic kernel
Generic platform:
- yamon-dt: Pull YAMON DT shim code out of SEAD-3 board
- yamon-dt: Support > 256MB of RAM
- yamon-dt: Use serial* rather than uart* aliases
- Abstract FDT fixup application
- Set RTC_ALWAYS_BCD to 0
- Add a MAINTAINERS entry
core kernel:
- qspinlock.c: include linux/prefetch.h
Loongson 3:
- Add support
Perf:
- Add I6500 support
SEAD-3:
- Remove GIC timer from DT
- Set interrupt-parent per-device, not at root node
- Fix GIC interrupt specifiers
SMP:
- Skip IPI setup if we only have a single CPU
VDSO:
- Make comment match reality
- Improvements to time code in VDSO"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits)
locking/qspinlock: Include linux/prefetch.h
MIPS: Fix MIPS I ISA /proc/cpuinfo reporting
MIPS: Fix minimum alignment requirement of IRQ stack
MIPS: generic: Support MIPS Boston development boards
MIPS: DTS: img: Don't attempt to build-in all .dtb files
clk: boston: Add a driver for MIPS Boston board clocks
dt-bindings: Document img,boston-clock binding
MIPS: Traced negative syscalls should return -ENOSYS
MIPS: Correct forced syscall errors
MIPS: Negate error syscall return in trace
MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select
MIPS16e2: Provide feature overrides for non-MIPS16 systems
MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo
MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions
MIPS: MIPS16e2: Identify ASE presence
MIPS: VDSO: Fix a mismatch between comment and preprocessor constant
MIPS: VDSO: Add implementation of gettimeofday() fallback
MIPS: VDSO: Add implementation of clock_gettime() fallback
MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse()
MIPS: Use current_cpu_type() in m4kc_tlbp_war()
...
このコミットが含まれているのは:
Linus Torvalds
@@ -1,6 +1,7 @@
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dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb
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dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += boston.dtb
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obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
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dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb
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obj-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb.o
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# Force kbuild to make empty built-in.o if necessary
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obj- += dummy.o
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224
arch/mips/boot/dts/img/boston.dts
ノーマルファイル
224
arch/mips/boot/dts/img/boston.dts
ノーマルファイル
@@ -0,0 +1,224 @@
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/dts-v1/;
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#include <dt-bindings/clock/boston-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "img,boston";
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chosen {
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stdout-path = "uart0:115200";
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};
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aliases {
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uart0 = &uart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "img,mips";
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reg = <0>;
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clocks = <&clk_boston BOSTON_CLK_CPU>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x10000000>;
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};
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pci0: pci@10000000 {
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compatible = "xlnx,axi-pcie-host-1.00.a";
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device_type = "pci";
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reg = <0x10000000 0x2000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
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ranges = <0x02000000 0 0x40000000
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0x40000000 0 0x40000000>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pci0_intc 1>,
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<0 0 0 2 &pci0_intc 2>,
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<0 0 0 3 &pci0_intc 3>,
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<0 0 0 4 &pci0_intc 4>;
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pci0_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pci1: pci@12000000 {
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compatible = "xlnx,axi-pcie-host-1.00.a";
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device_type = "pci";
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reg = <0x12000000 0x2000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
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ranges = <0x02000000 0 0x20000000
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0x20000000 0 0x20000000>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pci1_intc 1>,
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<0 0 0 2 &pci1_intc 2>,
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<0 0 0 3 &pci1_intc 3>,
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<0 0 0 4 &pci1_intc 4>;
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pci1_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pci2: pci@14000000 {
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compatible = "xlnx,axi-pcie-host-1.00.a";
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device_type = "pci";
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reg = <0x14000000 0x2000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;
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ranges = <0x02000000 0 0x16000000
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0x16000000 0 0x100000>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pci2_intc 1>,
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<0 0 0 2 &pci2_intc 2>,
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<0 0 0 3 &pci2_intc 3>,
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<0 0 0 4 &pci2_intc 4>;
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pci2_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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pci2_root@0,0,0 {
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compatible = "pci10ee,7021";
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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eg20t_bridge@1,0,0 {
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compatible = "pci8086,8800";
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reg = <0x00010000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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eg20t_mac@2,0,1 {
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compatible = "pci8086,8802";
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reg = <0x00020100 0 0 0 0>;
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phy-reset-gpios = <&eg20t_gpio 6
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GPIO_ACTIVE_LOW>;
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};
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eg20t_gpio: eg20t_gpio@2,0,2 {
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compatible = "pci8086,8803";
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reg = <0x00020200 0 0 0 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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eg20t_i2c@2,12,2 {
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compatible = "pci8086,8817";
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reg = <0x00026200 0 0 0 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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rtc@0x68 {
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compatible = "st,m41t81s";
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reg = <0x68>;
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};
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};
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};
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};
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};
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gic: interrupt-controller@16120000 {
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compatible = "mti,gic";
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reg = <0x16120000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&clk_boston BOSTON_CLK_CPU>;
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};
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};
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cdmm@16140000 {
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compatible = "mti,mips-cdmm";
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reg = <0x16140000 0x8000>;
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};
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cpc@16200000 {
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compatible = "mti,mips-cpc";
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reg = <0x16200000 0x8000>;
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};
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plat_regs: system-controller@17ffd000 {
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compatible = "img,boston-platform-regs", "syscon";
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reg = <0x17ffd000 0x1000>;
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clk_boston: clock {
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compatible = "img,boston-clock";
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#clock-cells = <1>;
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};
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};
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reboot: syscon-reboot {
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compatible = "syscon-reboot";
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regmap = <&plat_regs>;
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offset = <0x10>;
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mask = <0x10>;
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};
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uart0: uart@17ffe000 {
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compatible = "ns16550a";
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reg = <0x17ffe000 0x1000>;
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reg-shift = <2>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_boston BOSTON_CLK_SYS>;
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};
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lcd: lcd@17fff000 {
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compatible = "img,boston-lcd";
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reg = <0x17fff000 0x8>;
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};
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};
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@@ -11,15 +11,14 @@
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#size-cells = <1>;
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compatible = "mti,sead-3";
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model = "MIPS SEAD-3";
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interrupt-parent = <&gic>;
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chosen {
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stdout-path = "uart1:115200";
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stdout-path = "serial1:115200";
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};
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aliases {
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uart0 = &uart0;
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uart1 = &uart1;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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cpus {
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@@ -54,18 +53,14 @@
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* controller & should be probed first.
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*/
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interrupt-parent = <&cpu_intc>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
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};
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};
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ehci@1b200000 {
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compatible = "generic-ehci";
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reg = <0x1b200000 0x1000>;
|
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interrupts = <0>; /* GIC 0 or CPU 6 */
|
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interrupt-parent = <&gic>;
|
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interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
|
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has-transaction-translator;
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};
|
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@@ -227,7 +222,8 @@
|
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clock-frequency = <14745600>;
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interrupts = <3>; /* GIC 3 or CPU 4 */
|
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interrupt-parent = <&gic>;
|
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interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
|
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|
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no-loopback-test;
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};
|
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@@ -241,7 +237,8 @@
|
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|
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clock-frequency = <14745600>;
|
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|
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interrupts = <2>; /* GIC 2 or CPU 4 */
|
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interrupt-parent = <&gic>;
|
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interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
|
||||
|
||||
no-loopback-test;
|
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};
|
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@@ -251,7 +248,8 @@
|
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reg = <0x1f010000 0x10000>;
|
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reg-io-width = <4>;
|
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|
||||
interrupts = <0>; /* GIC 0 or CPU 6 */
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
|
||||
|
||||
phy-mode = "mii";
|
||||
smsc,irq-push-pull;
|
||||
|
||||
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