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arm64: lockref: add support for lockless lockrefs using cmpxchg

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Our spinlocks are only 32-bit (2x16-bit tickets) and our cmpxchg can
deal with 8-bytes (as one would hope!).

This patch wires up the cmpxchg-based lockless lockref implementation
for arm64.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Will Deacon
2013-10-09 15:54:27 +01:00
committed by Catalin Marinas
parent 52ea2a560a
commit 5686b06cea
2 changed files with 7 additions and 2 deletions
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8
arch/arm64/include/asm/spinlock.h
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@@ -92,10 +92,14 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
: "memory");
}
static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
{
return lock.owner == lock.next;
}
static inline int arch_spin_is_locked(arch_spinlock_t *lock)
{
arch_spinlock_t lockval = ACCESS_ONCE(*lock);
return lockval.owner != lockval.next;
return !arch_spin_value_unlocked(ACCESS_ONCE(*lock));
}
static inline int arch_spin_is_contended(arch_spinlock_t *lock)