sh: intc - add support for SH7750 and its variants
This patch converts the cpu specific 7750 setup code to use the new intc controller. Many new vectors are added and multiple processor variants including 7091, 7750, 7750s, 7750r, 7751 and 7751r should all have the correct vectors hooked up. IRLM interrupts can be enabled using ipr_irq_enable_irlm() which now is marked as __init. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
@@ -82,88 +82,213 @@ static int __init sh7750_devices_setup(void)
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}
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__initcall(sh7750_devices_setup);
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static struct ipr_data ipr_irq_table[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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{ 17, 0, 12, 2 }, /* TMU1 TUNI */
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{ 18, 0, 4, 2 }, /* TMU2 TUNI */
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{ 19, 0, 4, 2 }, /* TMU2 TIPCI */
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{ 27, 1, 12, 2 }, /* WDT ITI */
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{ 20, 0, 0, 2 }, /* RTC ATI (alarm) */
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{ 21, 0, 0, 2 }, /* RTC PRI (period) */
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{ 22, 0, 0, 2 }, /* RTC CUI (carry) */
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{ 23, 1, 4, 3 }, /* SCI ERI */
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{ 24, 1, 4, 3 }, /* SCI RXI */
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{ 25, 1, 4, 3 }, /* SCI TXI */
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{ 40, 2, 4, 3 }, /* SCIF ERI */
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{ 41, 2, 4, 3 }, /* SCIF RXI */
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{ 42, 2, 4, 3 }, /* SCIF BRI */
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{ 43, 2, 4, 3 }, /* SCIF TXI */
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{ 34, 2, 8, 7 }, /* DMAC DMTE0 */
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{ 35, 2, 8, 7 }, /* DMAC DMTE1 */
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{ 36, 2, 8, 7 }, /* DMAC DMTE2 */
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{ 37, 2, 8, 7 }, /* DMAC DMTE3 */
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{ 38, 2, 8, 7 }, /* DMAC DMAE */
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
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HUDI, GPIOI,
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DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
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DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
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DMAC_DMAE,
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PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
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TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
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RTC_ATI, RTC_PRI, RTC_CUI,
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SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
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SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
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WDT,
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REF_RCMI, REF_ROVI,
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/* interrupt groups */
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DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
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};
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static unsigned long ipr_offsets[] = {
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0xffd00004UL, /* 0: IPRA */
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0xffd00008UL, /* 1: IPRB */
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0xffd0000cUL, /* 2: IPRC */
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0xffd00010UL, /* 3: IPRD */
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static struct intc_vect vectors[] = {
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INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
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INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
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INTC_VECT(RTC_CUI, 0x4c0),
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INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
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INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
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INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
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INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
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};
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static struct ipr_desc ipr_irq_desc = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table),
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.chip = {
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.name = "IPR-sh7750",
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},
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static struct intc_group groups[] = {
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INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
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INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
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INTC_GROUP(REF, REF_RCMI, REF_ROVI),
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};
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#ifdef CONFIG_CPU_SUBTYPE_SH7751
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static struct ipr_data ipr_irq_table_sh7751[] = {
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{ 44, 2, 8, 7 }, /* DMAC DMTE4 */
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{ 45, 2, 8, 7 }, /* DMAC DMTE5 */
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{ 46, 2, 8, 7 }, /* DMAC DMTE6 */
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{ 47, 2, 8, 7 }, /* DMAC DMTE7 */
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/* The following use INTC_INPRI00 for masking, which is a 32-bit
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register, not a 16-bit register like the IPRx registers, so it
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would need special support */
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/*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */
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/*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */
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static struct intc_prio priorities[] = {
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INTC_PRIO(SCIF, 3),
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INTC_PRIO(SCI1, 3),
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INTC_PRIO(DMAC, 7),
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};
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static struct ipr_desc ipr_irq_desc_sh7751 = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table_sh7751,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table_sh7751),
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.chip = {
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.name = "IPR-sh7751",
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},
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static struct intc_prio_reg prio_registers[] = {
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{ 0xffd00004, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xffd00008, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
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{ 0xffd0000c, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
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{ 0xffd00010, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
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{ 0xfe080000, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
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TMU4, TMU3,
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PCIC1, PCIC0_PCISERR } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
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priorities, NULL, prio_registers, NULL);
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/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7091)
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static struct intc_vect vectors_dma4[] = {
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INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
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INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
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INTC_VECT(DMAC_DMAE, 0x6c0),
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};
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static struct intc_group groups_dma4[] = {
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INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
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DMAC_DMTE3, DMAC_DMAE),
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};
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static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
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vectors_dma4, groups_dma4,
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priorities, NULL, prio_registers, NULL);
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#endif
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/* SH7750R and SH7751R both have 8-channel DMA controllers */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_dma8[] = {
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INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
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INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
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INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
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INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
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INTC_VECT(DMAC_DMAE, 0x6c0),
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};
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static struct intc_group groups_dma8[] = {
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INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
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DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
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DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
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};
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static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
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vectors_dma8, groups_dma8,
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priorities, NULL, prio_registers, NULL);
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#endif
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/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_tmu34[] = {
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INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
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};
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static struct intc_mask_reg mask_registers[] = {
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{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, TMU4, TMU3,
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PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
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PCIC1_PCIDMA3, PCIC0_PCISERR } },
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};
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static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
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vectors_tmu34, NULL, priorities,
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mask_registers, prio_registers, NULL);
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#endif
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/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
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static struct intc_vect vectors_irlm[] = {
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INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
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INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
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};
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static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
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priorities, NULL, prio_registers, NULL);
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/* SH7751 and SH7751R both have PCI */
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#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_pci[] = {
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INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
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INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
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INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
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INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
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};
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static struct intc_group groups_pci[] = {
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INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
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};
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static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
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priorities, mask_registers, prio_registers, NULL);
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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defined(CONFIG_CPU_SUBTYPE_SH7091)
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void __init plat_irq_setup(void)
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{
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register_ipr_controller(&ipr_irq_desc);
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#ifdef CONFIG_CPU_SUBTYPE_SH7751
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register_ipr_controller(&ipr_irq_desc_sh7751);
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#endif
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/*
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* same vectors for SH7750, SH7750S and SH7091 except for IRLM,
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* see below..
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*/
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register_intc_controller(&intc_desc);
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register_intc_controller(&intc_desc_dma4);
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}
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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register_intc_controller(&intc_desc_dma8);
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register_intc_controller(&intc_desc_tmu34);
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}
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7751)
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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register_intc_controller(&intc_desc_dma4);
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register_intc_controller(&intc_desc_tmu34);
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register_intc_controller(&intc_desc_pci);
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}
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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register_intc_controller(&intc_desc_dma8);
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register_intc_controller(&intc_desc_tmu34);
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register_intc_controller(&intc_desc_pci);
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}
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#endif
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#define INTC_ICR 0xffd00000UL
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#define INTC_ICR_IRLM (1<<7)
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/* enable individual interrupt mode for external interupts */
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void ipr_irq_enable_irlm(void)
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void __init ipr_irq_enable_irlm(void)
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{
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
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BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
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#endif
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register_intc_controller(&intc_desc_irlm);
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ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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}
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