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ARM: meson: DTS: enable L2 cache

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This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
This commit is contained in:
Beniamino Galvani
2014-11-18 15:30:35 +01:00
committed by Carlo Caione
parent aeff05a39a
commit 550ab390d7
3 changed files with 13 additions and 0 deletions
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arch/arm/boot/dts/meson6.dtsi
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@@ -60,12 +60,14 @@
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x200>;
};
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x201>;
};
};