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Merge branch 'clk-next' into v3.19-rc7

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This commit is contained in:
Michael Turquette
2015-02-02 14:59:38 -08:00
parent e36f014edf b530e7d210
commit 54eea32f7e
117 changed files with 12333 additions and 5273 deletions
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97
include/dt-bindings/clock/alphascale,asm9260.h Normal file
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@@ -0,0 +1,97 @@
/*
* Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_ASM9260_H
#define _DT_BINDINGS_CLK_ASM9260_H
/* ahb gate */
#define CLKID_AHB_ROM 0
#define CLKID_AHB_RAM 1
#define CLKID_AHB_GPIO 2
#define CLKID_AHB_MAC 3
#define CLKID_AHB_EMI 4
#define CLKID_AHB_USB0 5
#define CLKID_AHB_USB1 6
#define CLKID_AHB_DMA0 7
#define CLKID_AHB_DMA1 8
#define CLKID_AHB_UART0 9
#define CLKID_AHB_UART1 10
#define CLKID_AHB_UART2 11
#define CLKID_AHB_UART3 12
#define CLKID_AHB_UART4 13
#define CLKID_AHB_UART5 14
#define CLKID_AHB_UART6 15
#define CLKID_AHB_UART7 16
#define CLKID_AHB_UART8 17
#define CLKID_AHB_UART9 18
#define CLKID_AHB_I2S0 19
#define CLKID_AHB_I2C0 20
#define CLKID_AHB_I2C1 21
#define CLKID_AHB_SSP0 22
#define CLKID_AHB_IOCONFIG 23
#define CLKID_AHB_WDT 24
#define CLKID_AHB_CAN0 25
#define CLKID_AHB_CAN1 26
#define CLKID_AHB_MPWM 27
#define CLKID_AHB_SPI0 28
#define CLKID_AHB_SPI1 29
#define CLKID_AHB_QEI 30
#define CLKID_AHB_QUADSPI0 31
#define CLKID_AHB_CAMIF 32
#define CLKID_AHB_LCDIF 33
#define CLKID_AHB_TIMER0 34
#define CLKID_AHB_TIMER1 35
#define CLKID_AHB_TIMER2 36
#define CLKID_AHB_TIMER3 37
#define CLKID_AHB_IRQ 38
#define CLKID_AHB_RTC 39
#define CLKID_AHB_NAND 40
#define CLKID_AHB_ADC0 41
#define CLKID_AHB_LED 42
#define CLKID_AHB_DAC0 43
#define CLKID_AHB_LCD 44
#define CLKID_AHB_I2S1 45
#define CLKID_AHB_MAC1 46
/* devider */
#define CLKID_SYS_CPU 47
#define CLKID_SYS_AHB 48
#define CLKID_SYS_I2S0M 49
#define CLKID_SYS_I2S0S 50
#define CLKID_SYS_I2S1M 51
#define CLKID_SYS_I2S1S 52
#define CLKID_SYS_UART0 53
#define CLKID_SYS_UART1 54
#define CLKID_SYS_UART2 55
#define CLKID_SYS_UART3 56
#define CLKID_SYS_UART4 56
#define CLKID_SYS_UART5 57
#define CLKID_SYS_UART6 58
#define CLKID_SYS_UART7 59
#define CLKID_SYS_UART8 60
#define CLKID_SYS_UART9 61
#define CLKID_SYS_SPI0 62
#define CLKID_SYS_SPI1 63
#define CLKID_SYS_QUADSPI 64
#define CLKID_SYS_SSP0 65
#define CLKID_SYS_NAND 66
#define CLKID_SYS_TRACE 67
#define CLKID_SYS_CAMM 68
#define CLKID_SYS_WDT 69
#define CLKID_SYS_CLKOUT 70
#define CLKID_SYS_MAC 71
#define CLKID_SYS_LCD 72
#define CLKID_SYS_ADCANA 73
#define MAX_CLKS 74
#endif

7
include/dt-bindings/clock/exynos4.h
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@@ -262,8 +262,13 @@
#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
#define CLK_DIV_ACP 456
#define CLK_DIV_DMC 457
#define CLK_DIV_C2C 458 /* Exynos4x12 only */
#define CLK_DIV_GDL 459
#define CLK_DIV_GDR 460
/* must be greater than maximal clock id */
#define CLK_NR_CLKS 456
#define CLK_NR_CLKS 461
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */

88
include/dt-bindings/clock/exynos7-clk.h
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@@ -17,7 +17,11 @@
#define DOUT_SCLK_CC_PLL 4
#define DOUT_SCLK_MFC_PLL 5
#define DOUT_ACLK_CCORE_133 6
#define TOPC_NR_CLK 7
#define DOUT_ACLK_MSCL_532 7
#define ACLK_MSCL_532 8
#define DOUT_SCLK_AUD_PLL 9
#define FOUT_AUD_PLL 10
#define TOPC_NR_CLK 11
/* TOP0 */
#define DOUT_ACLK_PERIC1 1
@@ -26,7 +30,15 @@
#define CLK_SCLK_UART1 4
#define CLK_SCLK_UART2 5
#define CLK_SCLK_UART3 6
#define TOP0_NR_CLK 7
#define CLK_SCLK_SPI0 7
#define CLK_SCLK_SPI1 8
#define CLK_SCLK_SPI2 9
#define CLK_SCLK_SPI3 10
#define CLK_SCLK_SPI4 11
#define CLK_SCLK_SPDIF 12
#define CLK_SCLK_PCM1 13
#define CLK_SCLK_I2S1 14
#define TOP0_NR_CLK 15
/* TOP1 */
#define DOUT_ACLK_FSYS1_200 1
@@ -70,7 +82,23 @@
#define PCLK_HSI2C6 9
#define PCLK_HSI2C7 10
#define PCLK_HSI2C8 11
#define PERIC1_NR_CLK 12
#define PCLK_SPI0 12
#define PCLK_SPI1 13
#define PCLK_SPI2 14
#define PCLK_SPI3 15
#define PCLK_SPI4 16
#define SCLK_SPI0 17
#define SCLK_SPI1 18
#define SCLK_SPI2 19
#define SCLK_SPI3 20
#define SCLK_SPI4 21
#define PCLK_I2S1 22
#define PCLK_PCM1 23
#define PCLK_SPDIF 24
#define SCLK_I2S1 25
#define SCLK_PCM1 26
#define SCLK_SPDIF 27
#define PERIC1_NR_CLK 28
/* PERIS */
#define PCLK_CHIPID 1
@@ -82,11 +110,63 @@
/* FSYS0 */
#define ACLK_MMC2 1
#define FSYS0_NR_CLK 2
#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
#define ACLK_USBDRD300 3
#define SCLK_USBDRD300_SUSPENDCLK 4
#define SCLK_USBDRD300_REFCLK 5
#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
#define ACLK_PDMA0 9
#define ACLK_PDMA1 10
#define FSYS0_NR_CLK 11
/* FSYS1 */
#define ACLK_MMC1 1
#define ACLK_MMC0 2
#define FSYS1_NR_CLK 3
/* MSCL */
#define USERMUX_ACLK_MSCL_532 1
#define DOUT_PCLK_MSCL 2
#define ACLK_MSCL_0 3
#define ACLK_MSCL_1 4
#define ACLK_JPEG 5
#define ACLK_G2D 6
#define ACLK_LH_ASYNC_SI_MSCL_0 7
#define ACLK_LH_ASYNC_SI_MSCL_1 8
#define ACLK_AXI2ACEL_BRIDGE 9
#define ACLK_XIU_MSCLX_0 10
#define ACLK_XIU_MSCLX_1 11
#define ACLK_QE_MSCL_0 12
#define ACLK_QE_MSCL_1 13
#define ACLK_QE_JPEG 14
#define ACLK_QE_G2D 15
#define ACLK_PPMU_MSCL_0 16
#define ACLK_PPMU_MSCL_1 17
#define ACLK_MSCLNP_133 18
#define ACLK_AHB2APB_MSCL0P 19
#define ACLK_AHB2APB_MSCL1P 20
#define PCLK_MSCL_0 21
#define PCLK_MSCL_1 22
#define PCLK_JPEG 23
#define PCLK_G2D 24
#define PCLK_QE_MSCL_0 25
#define PCLK_QE_MSCL_1 26
#define PCLK_QE_JPEG 27
#define PCLK_QE_G2D 28
#define PCLK_PPMU_MSCL_0 29
#define PCLK_PPMU_MSCL_1 30
#define PCLK_AXI2ACEL_BRIDGE 31
#define PCLK_PMU_MSCL 32
#define MSCL_NR_CLK 33
/* AUD */
#define SCLK_I2S 1
#define SCLK_PCM 2
#define PCLK_I2S 3
#define PCLK_PCM 4
#define ACLK_ADMA 5
#define AUD_NR_CLK 6
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */

1
include/dt-bindings/clock/qcom,gcc-ipq806x.h
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@@ -238,7 +238,6 @@
#define PLL0_VOTE 221
#define PLL3 222
#define PLL3_VOTE 223
#define PLL4 224
#define PLL4_VOTE 225
#define PLL8 226
#define PLL8_VOTE 227

30
include/dt-bindings/clock/qcom,lcc-ipq806x.h Normal file
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@@ -0,0 +1,30 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
#define _DT_BINDINGS_CLK_LCC_IPQ806X_H
#define PLL4 0
#define MI2S_OSR_SRC 1
#define MI2S_OSR_CLK 2
#define MI2S_DIV_CLK 3
#define MI2S_BIT_DIV_CLK 4
#define MI2S_BIT_CLK 5
#define PCM_SRC 6
#define PCM_CLK_OUT 7
#define PCM_CLK 8
#define SPDIF_SRC 9
#define SPDIF_CLK 10
#define AHBIX_CLK 11
#endif

50
include/dt-bindings/clock/qcom,lcc-msm8960.h Normal file
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@@ -0,0 +1,50 @@
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
#define _DT_BINDINGS_CLK_LCC_MSM8960_H
#define PLL4 0
#define MI2S_OSR_SRC 1
#define MI2S_OSR_CLK 2
#define MI2S_DIV_CLK 3
#define MI2S_BIT_DIV_CLK 4
#define MI2S_BIT_CLK 5
#define PCM_SRC 6
#define PCM_CLK_OUT 7
#define PCM_CLK 8
#define SLIMBUS_SRC 9
#define AUDIO_SLIMBUS_CLK 10
#define SPS_SLIMBUS_CLK 11
#define CODEC_I2S_MIC_OSR_SRC 12
#define CODEC_I2S_MIC_OSR_CLK 13
#define CODEC_I2S_MIC_DIV_CLK 14
#define CODEC_I2S_MIC_BIT_DIV_CLK 15
#define CODEC_I2S_MIC_BIT_CLK 16
#define SPARE_I2S_MIC_OSR_SRC 17
#define SPARE_I2S_MIC_OSR_CLK 18
#define SPARE_I2S_MIC_DIV_CLK 19
#define SPARE_I2S_MIC_BIT_DIV_CLK 20
#define SPARE_I2S_MIC_BIT_CLK 21
#define CODEC_I2S_SPKR_OSR_SRC 22
#define CODEC_I2S_SPKR_OSR_CLK 23
#define CODEC_I2S_SPKR_DIV_CLK 24
#define CODEC_I2S_SPKR_BIT_DIV_CLK 25
#define CODEC_I2S_SPKR_BIT_CLK 26
#define SPARE_I2S_SPKR_OSR_SRC 27
#define SPARE_I2S_SPKR_OSR_CLK 28
#define SPARE_I2S_SPKR_DIV_CLK 29
#define SPARE_I2S_SPKR_BIT_DIV_CLK 30
#define SPARE_I2S_SPKR_BIT_CLK 31
#endif

4
include/dt-bindings/clock/rk3288-cru.h
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@@ -80,6 +80,9 @@
#define SCLK_SDIO0_SAMPLE 119
#define SCLK_SDIO1_SAMPLE 120
#define SCLK_EMMC_SAMPLE 121
#define SCLK_USBPHY480M_SRC 122
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
#define DCLK_VOP0 190
#define DCLK_VOP1 191
@@ -154,6 +157,7 @@
#define PCLK_PUBL0 365
#define PCLK_DDRUPCTL1 366
#define PCLK_PUBL1 367
#define PCLK_WDT 368
/* hclk gates */
#define HCLK_GPS 448