xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915: Adjust system agent voltage on CNL if required by DDI ports

Browse Source 
On CNL we may need to bump up the system agent voltage not only due
to CDCLK but also when driving DDI port with a sufficiently high clock.
To that end start tracking the minimum acceptable voltage for each crtc.
We do the tracking via crtcs because we don't have any kind of encoder
state. Also there's no downside to doing it this way, and it matches how
we track cdclk requirements on account of pixel rate.

v2: Allow disabled crtcs to use the min voltage
    Add IS_CNL check to intel_ddi_compute_min_voltage() since
    we're using CNL specific values there
    s/intel_compute_min_voltage/cnl_compute_min_voltage/ since
    the function makes hw specific assumptions about the voltage
    values
v3: Drop the test hack leftovers from skl_modeset_calc_cdclk()
v4: s/voltage/voltage_level/ (Rodrigo)
    Replace DPLL DVFS FIXMEs with an explanation why we don't
    do anything there (Rodrigo)

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-9-ville.syrjala@linux.intel.com
This commit is contained in:
Ville Syrjälä
2017-10-24 12:52:14 +03:00
parent 48469eced2
commit 53e9bf5e81
7 changed files with 89 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/i915/intel_ddi.c
View File

@@ -2542,6 +2542,13 @@ bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
return false;
}
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
struct intel_crtc_state *crtc_state)
{
if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
crtc_state->min_voltage_level = 2;
}
void intel_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2641,6 +2648,8 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
if (IS_GEN9_LP(dev_priv))
pipe_config->lane_lat_optim_mask =
bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
}
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
@@ -2667,6 +2676,8 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder,
bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
pipe_config->lane_count);
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
return ret;
}