Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and 'clk-debugfs' into clk-next

- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs

* clk-actions:
  MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
  clk: actions: Add Actions S500 SoC Reset Management Unit support
  dt-bindings: reset: Add binding constants for Actions S500 RMU
  clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
  dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
  clk: actions: Fix h_clk for Actions S500 SoC

* clk-rockchip:
  clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks
  clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328"
  clk: rockchip: use separate compatibles for rk3288w-cru
  dt-bindings: clocks: add rk3288w variant compatible
  clk: rockchip: Handle clock tree for rk3288w variant
  clk: rockchip: convert rk3036 pll type to use internal lock status
  clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout
  clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout

* clk-iproc:
  clk: iproc: round clock rate to the closest

* clk-intel:
  clk: intel: Avoid unnecessary memset by improving code
  clk: intel: Improve locking in the driver
  clk: intel: Use devm_clk_hw_register() instead of clk_hw_register()

* clk-debugfs:
  clk: Add support for enabling/disabling clocks from debugfs

drivers/clk/clk.c

@@ -3054,6 +3054,31 @@ static int clk_rate_set(void *data, u64 val)
 }
 
 #define clk_rate_mode	0644
+
+static int clk_prepare_enable_set(void *data, u64 val)
+{
+	struct clk_core *core = data;
+	int ret = 0;
+
+	if (val)
+		ret = clk_prepare_enable(core->hw->clk);
+	else
+		clk_disable_unprepare(core->hw->clk);
+
+	return ret;
+}
+
+static int clk_prepare_enable_get(void *data, u64 *val)
+{
+	struct clk_core *core = data;
+
+	*val = core->enable_count && core->prepare_count;
+	return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(clk_prepare_enable_fops, clk_prepare_enable_get,
+			 clk_prepare_enable_set, "%llu\n");
+
 #else
 #define clk_rate_set	NULL
 #define clk_rate_mode	0444
@@ -3231,6 +3256,10 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
 	debugfs_create_u32("clk_notifier_count", 0444, root, &core->notifier_count);
 	debugfs_create_file("clk_duty_cycle", 0444, root, core,
 			    &clk_duty_cycle_fops);
+#ifdef CLOCK_ALLOW_WRITE_DEBUGFS
+	debugfs_create_file("clk_prepare_enable", 0644, root, core,
+			    &clk_prepare_enable_fops);
+#endif
 
 	if (core->num_parents > 0)
 		debugfs_create_file("clk_parent", 0444, root, core,