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MIPS: ralink: add memory definition for MT7620

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Populate struct soc_info with the data that describes our RAM window.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5183/
This commit is contained in:
John Crispin
2013-04-14 09:55:29 +02:00
committed by Ralf Baechle
parent fe98f612a1
commit 51e3960784
2 changed files with 28 additions and 0 deletions
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8
arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -50,6 +50,14 @@
#define SYSCFG0_DRAM_TYPE_DDR1 1 #define SYSCFG0_DRAM_TYPE_DDR1 1
#define SYSCFG0_DRAM_TYPE_DDR2 2 #define SYSCFG0_DRAM_TYPE_DDR2 2
#define MT7620_DRAM_BASE 0x0
#define MT7620_SDRAM_SIZE_MIN 2
#define MT7620_SDRAM_SIZE_MAX 64
#define MT7620_DDR1_SIZE_MIN 32
#define MT7620_DDR1_SIZE_MAX 128
#define MT7620_DDR2_SIZE_MIN 32
#define MT7620_DDR2_SIZE_MAX 256
#define MT7620_GPIO_MODE_I2C BIT(0) #define MT7620_GPIO_MODE_I2C BIT(0)
#define MT7620_GPIO_MODE_UART0_SHIFT 2 #define MT7620_GPIO_MODE_UART0_SHIFT 2
#define MT7620_GPIO_MODE_UART0_MASK 0x7 #define MT7620_GPIO_MODE_UART0_MASK 0x7

20
arch/mips/ralink/mt7620.c
View File

@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
switch (dram_type) {
case SYSCFG0_DRAM_TYPE_SDRAM:
soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
break;
case SYSCFG0_DRAM_TYPE_DDR1:
soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
break;
case SYSCFG0_DRAM_TYPE_DDR2:
soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
break;
default:
BUG();
}
soc_info->mem_base = MT7620_DRAM_BASE;
} }