Merge tag 'v3.18-rc4' into drm-next
backmerge to get vmwgfx locking changes into next as the conflict with per-plane locking.
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@@ -2870,6 +2870,13 @@ intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
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ssize_t ret;
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int i;
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/*
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* Sometime we just get the same incorrect byte repeated
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* over the entire buffer. Doing just one throw away read
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* initially seems to "solve" it.
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*/
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drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
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for (i = 0; i < 3; i++) {
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ret = drm_dp_dpcd_read(aux, offset, buffer, size);
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if (ret == size)
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@@ -3815,9 +3822,10 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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}
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}
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/* Training Pattern 3 support */
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/* Training Pattern 3 support, both source and sink */
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if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
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intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
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intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
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(IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
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intel_dp->use_tps3 = true;
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DRM_DEBUG_KMS("Displayport TPS3 supported\n");
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} else
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@@ -4604,6 +4612,18 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
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if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
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intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
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if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
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/*
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* vdd off can generate a long pulse on eDP which
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* would require vdd on to handle it, and thus we
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* would end up in an endless cycle of
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* "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
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*/
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DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
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port_name(intel_dig_port->port));
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return false;
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}
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DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
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port_name(intel_dig_port->port),
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long_hpd ? "long" : "short");
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