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clk: meson: add mpll pre-divider

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mpll clocks parent can actually be divided by 1 or 2. So far, this
divider has always been set to 1, so the calculation was correct.
Now that we know it exists, model the tree correctly. If we ever get
a platform where the divider is different, we won't get into trouble

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Jerome Brunet
2018-02-19 12:21:44 +01:00
committed by Neil Armstrong
parent 093c3fac46
commit 513b67ac39
6 changed files with 65 additions and 13 deletions
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3
drivers/clk/meson/axg.h
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@@ -121,8 +121,9 @@
#define CLKID_MPLL1_DIV 66
#define CLKID_MPLL2_DIV 67
#define CLKID_MPLL3_DIV 68
#define CLKID_MPLL_PREDIV 70
#define NR_CLKS 70
#define NR_CLKS 71
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>