Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson: "New or improved SoC support: - add support for Atmel's SAMA5D2 SoC - add support for Freescale i.MX6UL - improved support for TI's DM814x platform - misc fixes and improvements for RockChip platforms - Marvell MVEBU suspend/resume support A few driver changes that ideally would belong in the drivers branch are also here (acked by appropriate maintainers): - power key input driver for Freescale platforms (svns) - RTC driver updates for Freescale platforms (svns/mxc) - clk fixes for TI DM814/816X + a bunch of other changes for various platforms" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: rockchip: pm: Fix PTR_ERR() argument ARM: imx: mach-imx6ul: Fix allmodconfig build clk: ti: fix for definition movement ARM: uniphier: drop v7_invalidate_l1 call at secondary entry memory: kill off set_irq_flags usage rtc: snvs: select option REGMAP_MMIO ARM: brcmstb: select ARCH_DMA_ADDR_T_64BIT for LPAE ARM: BCM: Enable ARM erratum 798181 for BRCMSTB ARM: OMAP2+: Fix power domain operations regression caused by 81xx ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend ARM: rockchip: set correct stabilization thresholds in suspend ARM: rockchip: rename osc_switch_to_32k variable ARM: imx6ul: add fec MAC refrence clock and phy fixup init ARM: imx6ul: add fec bits to GPR syscon definition rtc: mxc: add support of device tree dt-binding: document the binding for mxc rtc rtc: mxc: use a second rtc clock ARM: davinci: cp_intc: use IRQCHIP_SKIP_SET_WAKE instead of irq_set_wake callback soc: mediatek: Fix SCPSYS compilation ARM: at91/soc: add basic support for new sama5d2 SoC ...
This commit is contained in:
Linus Torvalds
@@ -27,6 +27,8 @@ compatible: must be one of:
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o "atmel,at91sam9xe"
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* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
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SoC family:
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o "atmel,sama5d2" shall be extended with the specific SoC compatible:
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- "atmel,sama5d27"
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o "atmel,sama5d3" shall be extended with the specific SoC compatible:
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- "atmel,sama5d31"
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- "atmel,sama5d33"
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@@ -305,12 +305,13 @@ Secure Non-Volatile Storage (SNVS) Node
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Node defines address range and the associated
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interrupt for the SNVS function. This function
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monitors security state information & reports
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security violations.
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security violations. This also included rtc,
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system power off and ON/OFF key.
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- compatible
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Usage: required
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Value type: <string>
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Definition: Must include "fsl,sec-v4.0-mon".
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Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
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- reg
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Usage: required
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@@ -341,7 +342,7 @@ Secure Non-Volatile Storage (SNVS) Node
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the child address, parent address, & length.
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- interrupts
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Usage: required
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Usage: optional
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Value type: <prop_encoded-array>
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Definition: Specifies the interrupts generated by this
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device. The value of the interrupts property
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@@ -358,7 +359,7 @@ Secure Non-Volatile Storage (SNVS) Node
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EXAMPLE
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sec_mon@314000 {
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compatible = "fsl,sec-v4.0-mon";
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compatible = "fsl,sec-v4.0-mon", "syscon";
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reg = <0x314000 0x1000>;
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ranges = <0 0x314000 0x1000>;
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interrupt-parent = <&mpic>;
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@@ -375,16 +376,72 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
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Value type: <string>
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Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
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- reg
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- interrupts
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the physical
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address and length of the SNVS LP configuration registers.
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Value type: <prop_encoded-array>
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Definition: Specifies the interrupts generated by this
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device. The value of the interrupts property
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consists of one interrupt specifier. The format
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of the specifier is defined by the binding document
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describing the node's interrupt parent.
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- regmap
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Usage: required
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Value type: <phandle>
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Definition: this is phandle to the register map node.
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- offset
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Usage: option
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value type: <u32>
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Definition: LP register offset. default it is 0x34.
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EXAMPLE
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sec_mon_rtc_lp@314000 {
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sec_mon_rtc_lp@1 {
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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reg = <0x34 0x58>;
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interrupts = <93 2>;
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regmap = <&snvs>;
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offset = <0x34>;
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};
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=====================================================================
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System ON/OFF key driver
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The snvs-pwrkey is designed to enable POWER key function which controlled
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by SNVS ONOFF, the driver can report the status of POWER key and wakeup
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system if pressed after system suspend.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: Mush include "fsl,sec-v4.0-pwrkey".
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- interrupts:
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Usage: required
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Value type: <prop_encoded-array>
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Definition: The SNVS ON/OFF interrupt number to the CPU(s).
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- linux,keycode:
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Usage: option
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Value type: <int>
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Definition: Keycode to emit, KEY_POWER by default.
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- wakeup-source:
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Usage: option
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Value type: <boo>
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Definition: Button can wake-up the system.
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- regmap:
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Usage: required:
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Value type: <phandle>
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Definition: this is phandle to the register map node.
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EXAMPLE:
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snvs-pwrkey@0x020cc000 {
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compatible = "fsl,sec-v4.0-pwrkey";
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regmap = <&snvs>;
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interrupts = <0 4 0x4>
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linux,keycode = <116>; /* KEY_POWER */
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wakeup;
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};
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=====================================================================
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@@ -460,12 +517,20 @@ FULL EXAMPLE
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compatible = "fsl,sec-v4.0-mon";
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reg = <0x314000 0x1000>;
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ranges = <0 0x314000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <93 2>;
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sec_mon_rtc_lp@34 {
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compatible = "fsl,sec-v4.0-mon-rtc-lp";
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reg = <0x34 0x58>;
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regmap = <&sec_mon>;
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offset = <0x34>;
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interrupts = <93 2>;
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};
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snvs-pwrkey@0x020cc000 {
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compatible = "fsl,sec-v4.0-pwrkey";
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regmap = <&sec_mon>;
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interrupts = <0 4 0x4>;
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linux,keycode = <116>; /* KEY_POWER */
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wakeup;
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};
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};
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1
Documentation/devicetree/bindings/input/snvs-pwrkey.txt
Normal file
1
Documentation/devicetree/bindings/input/snvs-pwrkey.txt
Normal file
@@ -0,0 +1 @@
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See Documentation/devicetree/bindings/crypto/fsl-sec4.txt
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26
Documentation/devicetree/bindings/rtc/rtc-mxc.txt
Normal file
26
Documentation/devicetree/bindings/rtc/rtc-mxc.txt
Normal file
@@ -0,0 +1,26 @@
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* Real Time Clock of the i.MX SoCs
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RTC controller for the i.MX SoCs
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Required properties:
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- compatible: Should be "fsl,imx1-rtc" or "fsl,imx21-rtc".
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: IRQ line for the RTC.
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- clocks: should contain two entries:
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* one for the input reference
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* one for the the SoC RTC
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- clock-names: should contain:
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* "ref" for the input reference clock
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* "ipg" for the SoC RTC clock
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Example:
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rtc@10007000 {
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compatible = "fsl,imx21-rtc";
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reg = <0x10007000 0x1000>;
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interrupts = <22>;
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clocks = <&clks IMX27_CLK_CKIL>,
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<&clks IMX27_CLK_RTC_IPG_GATE>;
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clock-names = "ref", "ipg";
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};
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41
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
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41
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
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@@ -0,0 +1,41 @@
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MediaTek SCPSYS
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===============
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The System Control Processor System (SCPSYS) has several power management
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related tasks in the system. The tasks include thermal measurement, dynamic
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voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
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The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
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domain control.
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The driver implements the Generic PM domain bindings described in
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power/power_domain.txt. It provides the power domains defined in
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include/dt-bindings/power/mt8173-power.h.
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Required properties:
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- compatible: Must be "mediatek,mt8173-scpsys"
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- #power-domain-cells: Must be 1
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- reg: Address range of the SCPSYS unit
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- infracfg: must contain a phandle to the infracfg controller
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- clock, clock-names: clocks according to the common clock binding.
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The clocks needed "mm" and "mfg". These are the
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clocks which hardware needs to be enabled before
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enabling certain power domains.
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Example:
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scpsys: scpsys@10006000 {
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#power-domain-cells = <1>;
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compatible = "mediatek,mt8173-scpsys";
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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clocks = <&clk26m>,
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<&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mfg", "mm";
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};
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Example consumer:
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afe: mt8173-afe-pcm@11220000 {
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compatible = "mediatek,mt8173-afe-pcm";
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power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
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};
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