tile PCI RC: support PCIe TRIO 0 MAC 0 on Gx72 system

On Tilera Gx72 systems, the logic for figuring out whether
a given port is root complex is slightly different.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

arch/tile/include/hv/drv_trio_intf.h

@@ -168,6 +168,9 @@ pcie_stream_intr_config_sel_t;
 struct pcie_trio_ports_property
 {
   struct pcie_port_property ports[TILEGX_TRIO_PCIES];
+
+  /** Set if this TRIO belongs to a Gx72 device. */
+  uint8_t is_gx72;
 };
 
 /* Flags indicating traffic class. */